00001 /****************************/ 00002 /* THIS IS OPEN SOURCE CODE */ 00003 /****************************/ 00004 00005 /* 00006 * File: map-atom.c 00007 * Author: Harald Servat 00008 * redcrash@gmail.com 00009 */ 00010 00011 #include "freebsd.h" 00012 #include "papiStdEventDefs.h" 00013 #include "map.h" 00014 00015 /**************************************************************************** 00016 ATOM SUBSTRATE 00017 ATOM SUBSTRATE 00018 ATOM SUBSTRATE 00019 ATOM SUBSTRATE 00020 ATOM SUBSTRATE 00021 ****************************************************************************/ 00022 00023 /* 00024 NativeEvent_Value_AtomProcessor must match AtomProcessor_info 00025 */ 00026 00027 Native_Event_LabelDescription_t AtomProcessor_info[] = 00028 { 00029 {"BACLEARS", "The number of times the front end is resteered."}, 00030 {"BOGUS_BR", "The number of byte sequences mistakenly detected as taken branch instructions."}, 00031 {"BR_BAC_MISSP_EXEC", "The number of branch instructions that were mispredicted when decoded."}, 00032 {"BR_CALL_MISSP_EXEC", "The number of mispredicted CALL instructions that were executed."}, 00033 {"BR_CALL_EXEC", "The number of CALL instructions executed."}, 00034 {"BR_CND_EXEC", "The number of conditional branches executed, but not necessarily retired."}, 00035 {"BR_CND_MISSP_EXEC", "The number of mispredicted conditional branches executed."}, 00036 {"BR_IND_CALL_EXEC", "The number of indirect CALL instructions executed."}, 00037 {"BR_IND_EXEC", "The number of indirect branch instructions executed."}, 00038 {"BR_IND_MISSP_EXEC", "The number of mispredicted indirect branch instructions executed."}, 00039 {"BR_INST_DECODED", "The number of branch instructions decoded."}, 00040 {"BR_INST_EXEC", "The number of branches executed, but not necessarily retired."}, 00041 {"BR_INST_RETIRED.ANY", "The number of branch instructions retired. This is an architectural performance event."}, 00042 {"BR_INST_RETIRED.ANY1", "The number of branch instructions retired that were mispredicted."}, 00043 {"BR_INST_RETIRED.MISPRED", "The number of mispredicted branch instructions retired. This is an architectural performance event."}, 00044 {"BR_INST_RETIRED.MISPRED_NOT_TAKEN", "The number of not taken branch instructions retired that were mispredicted."}, 00045 {"BR_INST_RETIRED.MISPRED_TAKEN", "The number taken branch instructions retired that were mispredicted."}, 00046 {"BR_INST_RETIRED.PRED_NOT_TAKEN", "The number of not taken branch instructions retired that were correctly predicted."}, 00047 {"BR_INST_RETIRED.PRED_TAKEN", "The number of taken branch instructions retired that were correctly predicted."}, 00048 {"BR_INST_RETIRED.TAKEN", "The number of taken branch instructions retired."}, 00049 {"BR_MISSP_EXEC", "The number of mispredicted branch instructions that were executed."}, 00050 {"BR_RET_MISSP_EXEC", "The number of mispredicted RET instructions executed."}, 00051 {"BR_RET_BAC_MISSP_EXEC", "The number of RET instructions executed that were mispredicted at decode time."}, 00052 {"BR_RET_EXEC", "The number of RET instructions executed."}, 00053 {"BR_TKN_BUBBLE_1", "The number of branch predicted taken with bubble 1."}, 00054 {"BR_TKN_BUBBLE_2", "The number of branch predicted taken with bubble 2."}, 00055 {"BUSQ_EMPTY", "The number of cycles during which the core did not have any pending transactions in the bus queue."}, 00056 {"BUS_BNR_DRV", "The number of Bus Not Ready signals asserted on the bus. This event is thread-independent."}, 00057 {"BUS_DATA_RCV", "The number of bus cycles during which the processor is receiving data. This event is thread-independent."}, 00058 {"BUS_DRDY_CLOCKS", "The number of bus cycles during which the Data Ready signal is asserted on the bus. This event is thread-independent."}, 00059 {"BUS_HIT_DRV", "The number of bus cycles during which the processor drives the HIT# pin. This event is thread-independent."}, 00060 {"BUS_HITM_DRV", "The number of bus cycles during which the processor drives the HITM# pin. This event is thread-independent."}, 00061 {"BUS_IO_WAIT", "The number of core cycles during which I/O requests wait in the bus queue."}, 00062 {"BUS_LOCK_CLOCKS", "The number of bus cycles during which the LOCK signal was asserted on the bus. This event is thread independent."}, 00063 {"BUS_REQUEST_OUTSTANDING", "The number of pending full cache line read transactions on the bus occuring in each cycle. This event is thread independent."}, 00064 {"BUS_TRANS_P", "The number of partial bus transactions."}, 00065 {"BUS_TRANS_IFETCH", "The number of instruction fetch full cache line bus transactions."}, 00066 {"BUS_TRANS_INVAL", "The number of invalidate bus transactions."}, 00067 {"BUS_TRANS_PWR", "The number of partial write bus transactions."}, 00068 {"BUS_TRANS_DEF", "The number of deferred bus transactions."}, 00069 {"BUS_TRANS_BURST", "The number of burst transactions."}, 00070 {"BUS_TRANS_MEM", "The number of memory bus transactions."}, 00071 {"BUS_TRANS_ANY", "The number of bus transactions of any kind."}, 00072 {"BUS_TRANS_BRD", "The number of burst read transactions."}, 00073 {"BUS_TRANS_IO", "The number of completed I/O bus transaactions due to IN and OUT instructions."}, 00074 {"BUS_TRANS_RFO", "The number of Read For Ownership bus transactions."}, 00075 {"BUS_TRANS_WB", "The number explicit writeback bus transactions due to dirty line evictions."}, 00076 {"CMP_SNOOP", "The number of times the L1 data cache is snooped by the other core in the same processor."}, 00077 {"CPU_CLK_UNHALTED.BUS", "The number of bus cycles when the core is not in the halt state. This is an architectural performance event."}, 00078 {"CPU_CLK_UNHALTED.CORE_P", "The number of core cycles while the core is not in a halt state. This is an architectural performance event."}, 00079 {"CPU_CLK_UNHALTED.NO_OTHER", "The number of bus cycles during which the core remains unhalted and the other core is halted."}, 00080 {"CYCLES_DIV_BUSY", "The number of cycles the divider is busy."}, 00081 {"CYCLES_INT_MASKED.CYCLES_INT_MASKED", "The number of cycles during which interrupts are disabled."}, 00082 {"CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", "The number of cycles during which there were pending interrupts while interrupts were disabled."}, 00083 {"CYCLES_L1I_MEM_STALLED", "The number of cycles for which an instruction fetch stalls."}, 00084 {"DATA_TLB_MISSES.DTLB_MISS", "The number of memory access that missed the Data TLB"}, 00085 {"DATA_TLB_MISSES.DTLB_MISS_LD", "The number of loads that missed the Data TLB."}, 00086 {"DATA_TLB_MISSES.DTLB_MISS_ST", "The number of stores that missed the Data TLB."}, 00087 {"DATA_TLB_MISSES.UTLB_MISS_LD", "The number of loads that missed the UTLB."}, 00088 {"DELAYED_BYPASS.FP", "The number of floating point operations that used data immediately after the data was generated by a non floating point execution unit."}, 00089 {"DELAYED_BYPASS.LOAD", "The number of delayed bypass penalty cycles that a load operation incurred."}, 00090 {"DELAYED_BYPASS.SIMD", "The number of times SIMD operations use data immediately after data, was generated by a non-SIMD execution unit."}, 00091 {"DIV", "The number of divide operations executed. This event is only available on PMC1."}, 00092 {"DIV.AR", "The number of divide operations retired."}, 00093 {"DIV.S", "The number of divide operations executed."}, 00094 {"DTLB_MISSES.ANY", "The number of Data TLB misses, including misses that result from speculative accesses."}, 00095 {"DTLB_MISSES.L0_MISS_LD", "The number of level 0 DTLB misses due to load operations."}, 00096 {"DTLB_MISSES.MISS_LD", "The number of Data TLB misses due to load operations."}, 00097 {"DTLB_MISSES.MISS_ST", "The number of Data TLB misses due to store operations."}, 00098 {"EIST_TRANS", "The number of Enhanced Intel SpeedStep Technology transitions."}, 00099 {"ESP.ADDITIONS", "The number of automatic additions to the esp register."}, 00100 {"ESP.SYNCH", "The number of times the esp register was explicitly used in an address expression after it is implicitly used by a PUSH or POP instruction."}, 00101 {"EXT_SNOOP", "The number of snoop responses to bus transactions."}, 00102 {"FP_ASSIST", "The number of floating point operations executed that needed a microcode assist, including speculatively executed instructions."}, 00103 {"FP_ASSIST.AR", "The number of floating point operations retired that needed a microcode assist."}, 00104 {"FP_COMP_OPS_EXE", "The number of floating point computational micro-ops executed. The event is available only on PMC0."}, 00105 {"FP_MMX_TRANS_TO_FP", "The number of transitions from MMX instructions to floating point instructions."}, 00106 {"FP_MMX_TRANS_TO_MMX", "The number of transitions from floating point instructions to MMX instructions."}, 00107 {"HW_INT_RCV", "The number of hardware interrupts recieved."}, 00108 {"ICACHE.ACCESSES", "The number of instruction fetches."}, 00109 {"ICACHE.MISSES", "The number of instruction fetches that miss the instruction cache."}, 00110 {"IDLE_DURING_DIV", "The number of cycles the divider is busy and no other execution unit or load operation was in progress. This event is available only on PMC0."}, 00111 {"ILD_STALL", "The number of cycles the instruction length decoder stalled due to a length changing prefix."}, 00112 {"INST_QUEUE.FULL", "The number of cycles during which the instruction queue is full."}, 00113 {"INST_RETIRED.ANY_P", "The number of instructions retired. This is an architectural performance event."}, 00114 {"INST_RETIRED.LOADS", "The number of instructions retired that contained a load operation."}, 00115 {"INST_RETIRED.OTHER", "The number of instructions retired that did not contain a load or a store operation."}, 00116 {"INST_RETIRED.STORES", "The number of instructions retired that contained a store operation."}, 00117 {"ITLB.FLUSH", "The number of ITLB flushes."}, 00118 {"ITLB.LARGE_MISS", "The number of instruction fetches from large pages that miss the ITLB."}, 00119 {"ITLB.MISSES", "The number of instruction fetches from both large and small pages that miss the ITLB."}, 00120 {"ITLB.SMALL_MISS", "The number of instruction fetches from small pages that miss the ITLB."}, 00121 {"ITLB_MISS_RETIRED", "The number of retired instructions that missed the ITLB when they were fetched."}, 00122 {"L1D_ALL_REF", "The number of references to L1 data cache counting loads and stores of to all memory types."}, 00123 {"L1D_ALL_CACHE_REF", "The number of data reads and writes to cacheable memory."}, 00124 {"L1D_CACHE_LOCK", "The number of locked reads from cacheable memory."}, 00125 {"L1D_CACHE_LOCK_DURATION", "The number of cycles during which any cache line is locked by any locking instruction."}, 00126 {"L1D_CACHE.LD", "The number of data reads from cacheable memory."}, 00127 {"L1D_CACHE.ST", "The number of data writes to cacheable memory."}, 00128 {"L1D_M_EVICT", "The number of modified cache lines evicted from L1 data cache."}, 00129 {"L1D_M_REPL", "The number of modified lines allocated in L1 data cache."}, 00130 {"L1D_PEND_MISS", "The total number of outstanding L1 data cache misses at any clock."}, 00131 {"L1D_PREFETCH.REQUESTS", "The number of times L1 data cache requested to prefetch a data cache line."}, 00132 {"L1D_REPL", "The number of lines brought into L1 data cache."}, 00133 {"L1D_SPLIT.LOADS", "The number of load operations that span two cache lines."}, 00134 {"L1D_SPLIT.STORES", "The number of store operations that span two cache lines."}, 00135 {"L1I_MISSES", "The number of instruction fetch unit misses."}, 00136 {"L1I_READS", "The number of instruction fetches."}, 00137 {"L2_ADS", "The number of cycles that the L2 address bus is in use."}, 00138 {"L2_DBUS_BUSY_RD", "The number of core cycles during which the L2 data bus is busy transferring data to the core."}, 00139 {"L2_IFETCH", "The number of instruction cache line requests from the instruction fetch unit."}, 00140 {"L2_LD", "The number of L2 cache read requests from L1 cache and L2 prefetchers."}, 00141 {"L2_LINES_IN", "The number of cache lines allocated in L2 cache."}, 00142 {"L2_LINES_OUT", "The number of L2 cache lines evicted."}, 00143 {"L2_LOCK", "The number of locked accesses to cache lines that miss L1 data cache."}, 00144 {"L2_M_LINES_IN", "The number of L2 cache line modifications."}, 00145 {"L2_M_LINES_OUT", "The number of modified lines evicted from L2 cache."}, 00146 {"L2_NO_REQ", "The number of cycles during which no L2 cache requests were pending from a core."}, 00147 {"L2_REJECT_BUSQ", "The number of L2 cache requests that were rejected."}, 00148 {"L2_RQSTS", "The number of completed L2 cache requests."}, 00149 {"L2_RQSTS.SELF.DEMAND.I_STATE", "The number of completed L2 cache demand requests from this core that missed the L2 cache. This is an architectural performance event."}, 00150 {"L2_RQSTS.SELF.DEMAND.MESI", "The number of completed L2 cache demand requests from this core."}, 00151 {"L2_ST", "The number of store operations that miss the L1 cache and request data from the L2 cache."}, 00152 {"LOAD_BLOCK.L1D", "The number of loads blocked by the L1 data cache."}, 00153 {"LOAD_BLOCK.OVERLAP_STORE", "The number of loads that partially overlap an earlier store or are aliased with a previous store."}, 00154 {"LOAD_BLOCK.STA", "The number of loads blocked by preceding stores whose address is yet to be calculated."}, 00155 {"LOAD_BLOCK.STD", "The number of loads blocked by preceding stores to the same address whose data value is not known."}, 00156 {"LOAD_BLOCK.UNTIL_RETIRE", "The numer of load operations that were blocked until retirement."}, 00157 {"LOAD_HIT_PRE", "The number of load operations that conflicted with an prefetch to the same cache line."}, 00158 {"MACHINE_CLEARS.SMC", "The number of times a program writes to a code section."}, 00159 {"MACHINE_NUKES.MEM_ORDER", "The number of times the execution pipeline was restarted due to a memory ordering conflict or memory disambiguation misprediction."}, 00160 {"MACRO_INSTS.ALL_DECODED", "The number of instructions decoded."}, 00161 {"MACRO_INSTS.CISC_DECODED", "The number of complex instructions decoded."}, 00162 {"MEMORY_DISAMBIGUATION.RESET", "The number of cycles during which memory disambiguation misprediction occurs."}, 00163 {"MEMORY_DISAMBIGUATION.SUCCESS", "The number of load operations that were successfully disambiguated."}, 00164 {"MEM_LOAD_RETIRED.DTLB_MISS", "The number of retired load operations that missed the DTLB."}, 00165 {"MEM_LOAD_RETIRED.L2_MISS", "The number of retired load operations that miss L2 cache."}, 00166 {"MEM_LOAD_RETIRED.L2_HIT", "The number of retired load operations that hit L2 cache."}, 00167 {"MEM_LOAD_RETIRED.L2_LINE_MISS", "The number of load operations that missed L2 cache and that caused a bus request."}, 00168 {"MUL", "The number of multiply operations executed. This event is only available on PMC1."}, 00169 {"MUL.AR", "The number of multiply operations retired."}, 00170 {"MUL.S", "The number of multiply operations executed."}, 00171 {"PAGE_WALKS.WALKS", "The number of page walks executed due to an ITLB or DTLB miss."}, 00172 {"PAGE_WALKS.CYCLES", "The number of cycles spent in a page walk caused by an ITLB or DTLB miss."}, 00173 {"PREF_RQSTS_DN", "The number of downward prefetches issued from the Data Prefetch Logic unit to L2 cache."}, 00174 {"PREF_RQSTS_UP", "The number of upward prefetches issued from the Data Prefetch Logic unit to L2 cache."}, 00175 {"PREFETCH.PREFETCHNTA", "The number of PREFETCHNTA instructions executed."}, 00176 {"PREFETCH.PREFETCHT0", "The number of PREFETCHT0 instructions executed."}, 00177 {"PREFETCH.SW_L2", "The number of PREFETCHT1 and PREFETCHT2 instructions executed."}, 00178 {"RAT_STALLS.ANY", "The number of stall cycles due to any of RAT_STALLS.FLAGS RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and RAT_STALLS.ROB_READ_PORT."}, 00179 {"RAT_STALLS.FLAGS", "The number of cycles execution stalled due to a flag register induced stall."}, 00180 {"RAT_STALLS.FPSW", "The number of times the floating point status word was written."}, 00181 {"RAT_STALLS.PARTIAL_CYCLES", "The number of cycles of added instruction execution latency due to the use of a register that was partially written by previous instructions."}, 00182 {"RAT_STALLS.ROB_READ_PORT", "The number of cycles when ROB read port stalls occurred."}, 00183 {"RESOURCE_STALLS.ANY", "The number of cycles during which any resource related stall occurred."}, 00184 {"RESOURCE_STALLS.BR_MISS_CLEAR", "The number of cycles stalled due to branch misprediction."}, 00185 {"RESOURCE_STALLS.FPCW", "The number of cycles stalled due to writing the floating point control word."}, 00186 {"RESOURCE_STALLS.LD_ST", "The number of cycles during which the number of loads and stores in the pipeline exceeded their limits."}, 00187 {"RESOURCE_STALLS.ROB_FULL", "The number of cycles when the reorder buffer was full."}, 00188 {"RESOURCE_STALLS.RS_FULL", "The number of cycles during which the RS was full."}, 00189 {"RS_UOPS_DISPATCHED", "The number of micro-ops dispatched for execution."}, 00190 {"RS_UOPS_DISPATCHED.PORT0", "The number of cycles micro-ops were dispatched for execution on port 0."}, 00191 {"RS_UOPS_DISPATCHED.PORT1", "The number of cycles micro-ops were dispatched for execution on port 1."}, 00192 {"RS_UOPS_DISPATCHED.PORT2", "The number of cycles micro-ops were dispatched for execution on port 2."}, 00193 {"RS_UOPS_DISPATCHED.PORT3", "The number of cycles micro-ops were dispatched for execution on port 3."}, 00194 {"RS_UOPS_DISPATCHED.PORT4", "The number of cycles micro-ops were dispatched for execution on port 4."}, 00195 {"RS_UOPS_DISPATCHED.PORT5", "The number of cycles micro-ops were dispatched for execution on port 5."}, 00196 {"SB_DRAIN_CYCLES", "The number of cycles while the store buffer is draining."}, 00197 {"SEGMENT_REG_LOADS.ANY", "The number of segment register loads."}, 00198 {"SEG_REG_RENAMES.ANY", "The number of times the any segment register was renamed."}, 00199 {"SEG_REG_RENAMES.DS", "The number of times the ds register is renamed."}, 00200 {"SEG_REG_RENAMES.ES", "The number of times the es register is renamed."}, 00201 {"SEG_REG_RENAMES.FS", "The number of times the fs register is renamed."}, 00202 {"SEG_REG_RENAMES.GS", "The number of times the gs register is renamed."}, 00203 {"SEG_RENAME_STALLS.ANY", "The number of stalls due to lack of resource to rename any segment register."}, 00204 {"SEG_RENAME_STALLS.DS", "The number of stalls due to lack of renaming resources for the ds register."}, 00205 {"SEG_RENAME_STALLS.ES", "The number of stalls due to lack of renaming resources for the es register."}, 00206 {"SEG_RENAME_STALLS.FS", "The number of stalls due to lack of renaming resources for the fs register."}, 00207 {"SEG_RENAME_STALLS.GS", "The number of stalls due to lack of renaming resources for the gs register."}, 00208 {"SIMD_ASSIST", "The number SIMD assists invoked."}, 00209 {"SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", "Then number of computational SSE2 packed double precision instructions retired."}, 00210 {"SIMD_COMP_INST_RETIRED.PACKED_SINGLE", "Then number of computational SSE2 packed single precision instructions retired."}, 00211 {"SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", "Then number of computational SSE2 scalar double precision instructions retired."}, 00212 {"SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", "Then number of computational SSE2 scalar single precision instructions retired."}, 00213 {"SIMD_INSTR_RETIRED", "The number of retired SIMD instructions that use MMX registers."}, 00214 {"SIMD_INST_RETIRED.ANY", "The number of streaming SIMD instructions retired."}, 00215 {"SIMD_INST_RETIRED.PACKED_DOUBLE", "The number of SSE2 packed double precision instructions retired."}, 00216 {"SIMD_INST_RETIRED.PACKED_SINGLE", "The number of SSE packed single precision instructions retired."}, 00217 {"SIMD_INST_RETIRED.SCALAR_DOUBLE", "The number of SSE2 scalar double precision instructions retired."}, 00218 {"SIMD_INST_RETIRED.SCALAR_SINGLE", "The number of SSE scalar single precision instructions retired."}, 00219 {"SIMD_INST_RETIRED.VECTOR", "The number of SSE2 vector instructions retired."}, 00220 {"SIMD_SAT_INSTR_RETIRED", "The number of saturated arithmetic SIMD instructions retired."}, 00221 {"SIMD_SAT_UOP_EXEC.AR", "The number of SIMD saturated arithmetic micro-ops retired."}, 00222 {"SIMD_SAT_UOP_EXEC.S", "The number of SIMD saturated arithmetic micro-ops executed."}, 00223 {"SIMD_UOPS_EXEC.AR", "The number of SIMD micro-ops retired."}, 00224 {"SIMD_UOPS_EXEC.S", "The number of SIMD micro-ops executed."}, 00225 {"SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", "The number of SIMD packed arithmetic micro-ops executed."}, 00226 {"SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", "The number of SIMD packed arithmetic micro-ops executed."}, 00227 {"SIMD_UOP_TYPE_EXEC.LOGICAL.AR", "The number of SIMD packed logical microops executed."}, 00228 {"SIMD_UOP_TYPE_EXEC.LOGICAL.S", "The number of SIMD packed logical microops executed."}, 00229 {"SIMD_UOP_TYPE_EXEC.MUL.AR", "The number of SIMD packed multiply microops retired."}, 00230 {"SIMD_UOP_TYPE_EXEC.MUL.S", "The number of SIMD packed multiply microops executed."}, 00231 {"SIMD_UOP_TYPE_EXEC.PACK.AR", "The number of SIMD pack micro-ops retired."}, 00232 {"SIMD_UOP_TYPE_EXEC.PACK.S", "The number of SIMD pack micro-ops executed."}, 00233 {"SIMD_UOP_TYPE_EXEC.SHIFT.AR", "The number of SIMD packed shift micro-ops retired."}, 00234 {"SIMD_UOP_TYPE_EXEC.SHIFT.S", "The number of SIMD packed shift micro-ops executed."}, 00235 {"SIMD_UOP_TYPE_EXEC.UNPACK.AR", "The number of SIMD unpack micro-ops executed."}, 00236 {"SIMD_UOP_TYPE_EXEC.UNPACK.S", "The number of SIMD unpack micro-ops executed."}, 00237 {"SNOOP_STALL_DRV", "The number of times the bus stalled for snoops. This event is thread-independent."}, 00238 {"SSE_PRE_EXEC.L2", "The number of PREFETCHT1 instructions executed."}, 00239 {"SSE_PRE_EXEC.STORES", "The number of times SSE non-temporal store instructions were executed."}, 00240 {"SSE_PRE_MISS.L1", "The number of times the PREFETCHT0 instruction executed and missed all cache levels."}, 00241 {"SSE_PRE_MISS.L2", "The number of times the PREFETCHT1 instruction executed and missed all cache levels."}, 00242 {"SSE_PRE_MISS.NTA", "The number of times the PREFETCHNTA instruction executed and missed all cache levels."}, 00243 {"STORE_BLOCK.ORDER", "The number of cycles while a store was waiting for another store to be globally observed."}, 00244 {"STORE_BLOCK.SNOOP", "The number of cycles while a store was blocked due to a conflict with an internal or external snoop."}, 00245 {"STORE_FORWARDS.GOOD", "The number of times stored data was forwarded directly to a load."}, 00246 {"THERMAL_TRIP", "The number of thermal trips."}, 00247 {"UOPS_RETIRED.LD_IND_BR", "The number of micro-ops retired that fused a load with another operation."}, 00248 {"UOPS_RETIRED.STD_STA", "The number of store address calculations that fused into one micro-op."}, 00249 {"UOPS_RETIRED.MACRO_FUSION", "The number of times retired instruction pairs were fused into one micro-op."}, 00250 {"UOPS_RETIRED.FUSED", "The number of fused micro-ops retired."}, 00251 {"UOPS_RETIRED.NON_FUSED", "The number of non-fused micro-ops retired."}, 00252 {"UOPS_RETIRED.ANY", "The number of micro-ops retired."}, 00253 {"X87_COMP_OPS_EXE.ANY.AR", "The number of x87 floating-point computational micro-ops retired."}, 00254 {"X87_COMP_OPS_EXE.ANY.S", "The number of x87 floating-point computational micro-ops executed."}, 00255 {"X87_OPS_RETIRED.ANY", "The number of floating point computational instructions retired."}, 00256 {"X87_OPS_RETIRED.FXCH", "The number of FXCH instructions retired."}, 00257 { NULL, NULL } 00258 }; 00259

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