32 {
"BACLEARS",
"The number of times the front end is resteered."},
33 {
"BOGUS_BR",
"The number of byte sequences mistakenly detected as taken branch instructions."},
34 {
"BR_BAC_MISSP_EXEC",
"The number of branch instructions that were mispredicted when decoded."},
35 {
"BR_CALL_MISSP_EXEC",
"The number of mispredicted CALL instructions that were executed."},
36 {
"BR_CALL_EXEC",
"The number of CALL instructions executed."},
37 {
"BR_CND_EXEC",
"The number of conditional branches executed, but not necessarily retired."},
38 {
"BR_CND_MISSP_EXEC",
"The number of mispredicted conditional branches executed."},
39 {
"BR_IND_CALL_EXEC",
"The number of indirect CALL instructions executed."},
40 {
"BR_IND_EXEC",
"The number of indirect branch instructions executed."},
41 {
"BR_IND_MISSP_EXEC",
"The number of mispredicted indirect branch instructions executed."},
42 {
"BR_INST_DECODED",
"The number of branch instructions decoded."},
43 {
"BR_INST_EXEC",
"The number of branches executed, but not necessarily retired."},
44 {
"BR_INST_RETIRED.ANY",
"The number of branch instructions retired. This is an architectural performance event."},
45 {
"BR_INST_RETIRED.MISPRED",
"The number of mispredicted branch instructions retired. This is an architectural performance event."},
46 {
"BR_INST_RETIRED.MISPRED_NOT_TAKEN",
"The number of not taken branch instructions retired that were mispredicted."},
47 {
"BR_INST_RETIRED.MISPRED_TAKEN",
"The number taken branch instructions retired that were mispredicted."},
48 {
"BR_INST_RETIRED.PRED_NOT_TAKEN",
"The number of not taken branch instructions retired that were correctly predicted."},
49 {
"BR_INST_RETIRED.PRED_TAKEN",
"The number of taken branch instructions retired that were correctly predicted."},
50 {
"BR_INST_RETIRED.TAKEN",
"The number of taken branch instructions retired."},
51 {
"BR_MISSP_EXEC",
"The number of mispredicted branch instructions that were executed."},
52 {
"BR_RET_MISSP_EXEC",
"The number of mispredicted RET instructions executed."},
53 {
"BR_RET_BAC_MISSP_EXEC",
"The number of RET instructions executed that were mispredicted at decode time."},
54 {
"BR_RET_EXEC",
"The number of RET instructions executed."},
55 {
"BR_TKN_BUBBLE_1",
"The number of branch predicted taken with bubble 1."},
56 {
"BR_TKN_BUBBLE_2",
"The number of branch predicted taken with bubble 2."},
57 {
"BUSQ_EMPTY",
"The number of cycles during which the core did not have any pending transactions in the bus queue."},
58 {
"BUS_BNR_DRV",
"Number of Bus Not Ready signals asserted on the bus."},
59 {
"BUS_DATA_RCV",
"Number of bus cycles during which the processor is receiving data."},
60 {
"BUS_DRDY_CLOCKS",
"The number of bus cycles during which the Data Ready signal is asserted on the bus."},
61 {
"BUS_HIT_DRV",
"The number of bus cycles during which the processor drives the HIT# pin."},
62 {
"BUS_HITM_DRV",
"The number of bus cycles during which the processor drives the HITM# pin."},
63 {
"BUS_IO_WAIT",
"The number of core cycles during which I/O requests wait in the bus queue."},
64 {
"BUS_LOCK_CLOCKS",
"The number of bus cycles during which the LOCK signal was asserted on the bus."},
65 {
"BUS_REQUEST_OUTSTANDING",
"The number of pending full cache line read transactions on the bus occuring in each cycle."},
66 {
"BUS_TRANS_ANY",
"The number of bus transactions of any kind."},
67 {
"BUS_TRANS_BRD",
"The number of burst read transactions."},
68 {
"BUS_TRANS_BURST",
"The number of burst transactions."},
69 {
"BUS_TRANS_DEF",
"The number of deferred bus transactions."},
70 {
"BUS_TRANS_IFETCH",
"The number of instruction fetch full cache line bus transactions."},
71 {
"BUS_TRANS_INVAL",
"The number of invalidate bus transactions."},
72 {
"BUS_TRANS_IO",
"The number of completed I/O bus transaactions due to IN and OUT instructions."},
73 {
"BUS_TRANS_MEM",
"The number of memory bus transactions."},
74 {
"BUS_TRANS_P",
"The number of partial bus transactions."},
75 {
"BUS_TRANS_PWR",
"The number of partial write bus transactions."},
76 {
"BUS_TRANS_RFO",
"The number of Read For Ownership bus transactions."},
77 {
"BUS_TRANS_WB",
"The number of explicit writeback bus transactions due to dirty line evictions."},
78 {
"CMP_SNOOP",
"The number of times the L1 data cache is snooped by the other core in the same processor."},
79 {
"CPU_CLK_UNHALTED.BUS",
"The number of bus cycles when the core is not in the halt state. This is an architectural performance event."},
80 {
"CPU_CLK_UNHALTED.CORE_P",
"The number of core cycles while the core is not in a halt state. This is an architectural performance event."},
81 {
"CPU_CLK_UNHALTED.NO_OTHER",
"The number of bus cycles during which the core remains unhalted and the other core is halted."},
82 {
"CYCLES_DIV_BUSY",
"The number of cycles the divider is busy. This event is only available on PMC0."},
83 {
"CYCLES_INT_MASKED",
"The number of cycles during which interrupts are disabled."},
84 {
"CYCLES_INT_PENDING_AND_MASKED",
"The number of cycles during which there were pending interrupts while interrupts were disabled."},
85 {
"CYCLES_L1I_MEM_STALLED",
"The number of cycles for which an instruction fetch stalls."},
86 {
"DELAYED_BYPASS.FP",
"The number of floating point operations that used data immediately after the data was generated by a non floating point execution unit."},
87 {
"DELAYED_BYPASS.LOAD",
"The number of delayed bypass penalty cycles that a load operation incurred."},
88 {
"DELAYED_BYPASS.SIMD",
"The number of times SIMD operations use data immediately after data, was generated by a non-SIMD execution unit."},
89 {
"DIV",
"The number of divide operations executed."},
90 {
"DTLB_MISSES.ANY",
"The number of Data TLB misses, including misses that result from speculative accesses."},
91 {
"DTLB_MISSES.L0_MISS_LD",
"The number of level 0 DTLB misses due to load operations."},
92 {
"DTLB_MISSES.MISS_LD",
"The number of Data TLB misses due to load operations."},
93 {
"DTLB_MISSES.MISS_ST",
"The number of Data TLB misses due to store operations."},
94 {
"EIST_TRANS",
"The number of Enhanced Intel SpeedStep Technology transitions."},
95 {
"ESP.ADDITIONS",
"The number of automatic additions to the esp register."},
96 {
"ESP.SYNCH",
"The number of times the esp register was explicitly used in an address expression after it is implicitly used by a PUSH or POP instruction."},
97 {
"EXT_SNOOP",
"The number of snoop responses to bus transactions."},
98 {
"FP_ASSIST",
"The number of floating point operations executed that needed a microcode assist."},
99 {
"FP_COMP_OPS_EXE",
"The number of floating point computational micro-ops executed. The event is available only on PMC0."},
100 {
"FP_MMX_TRANS_TO_FP",
"The number of transitions from MMX instructions to floating point instructions."},
101 {
"FP_MMX_TRANS_TO_MMX",
"The number of transitions from floating point instructions to MMX instructions."},
102 {
"HW_INT_RCV",
"The number of hardware interrupts recieved."},
103 {
"IDLE_DURING_DIV",
"The number of cycles the divider is busy and no other execution unit or load operation was in progress. This event is available only on PMC0."},
104 {
"ILD_STALL",
"The number of cycles the instruction length decoder stalled due to a length changing prefix."},
105 {
"INST_QUEUE.FULL",
"The number of cycles during which the instruction queue is full."},
106 {
"INST_RETIRED.ANY_P",
"The number of instructions retired. This is an architectural performance event."},
107 {
"INST_RETIRED.LOADS",
"The number of instructions retired that contained a load operation."},
108 {
"INST_RETIRED.OTHER",
"The number of instructions retired that did not contain a load or a store operation."},
109 {
"INST_RETIRED.STORES",
"The number of instructions retired that contained a store operation."},
110 {
"ITLB.FLUSH",
"The number of ITLB flushes."},
111 {
"ITLB.LARGE_MISS",
"The number of instruction fetches from large pages that miss the ITLB."},
112 {
"ITLB.MISSES",
"The number of instruction fetches from both large and small pages that miss the ITLB."},
113 {
"ITLB.SMALL_MISS",
"The number of instruction fetches from small pages that miss the ITLB."},
114 {
"ITLB_MISS_RETIRED",
"The number of retired instructions that missed the ITLB when they were fetched."},
115 {
"L1D_ALL_CACHE_REF",
"The number of data reads and writes to cacheable memory."},
116 {
"L1D_ALL_REF",
"The number of references to L1 data cache counting loads and stores of to all memory types."},
117 {
"L1D_CACHE_LD",
"Number of data reads from cacheable memory excluding locked reads."},
118 {
"L1D_CACHE_LOCK",
"Number of locked reads from cacheable memory."},
119 {
"L1D_CACHE_LOCK_DURATION",
"The number of cycles during which any cache line is locked by any locking instruction."},
120 {
"L1D_CACHE_ST",
"The number of data writes to cacheable memory excluding locked writes."},
121 {
"L1D_M_EVICT",
"The number of modified cache lines evicted from L1 data cache."},
122 {
"L1D_M_REPL",
"The number of modified lines allocated in L1 data cache."},
123 {
"L1D_PEND_MISS",
"The total number of outstanding L1 data cache misses at any clock."},
124 {
"L1D_PREFETCH.REQUESTS",
"The number of times L1 data cache requested to prefetch a data cache line."},
125 {
"L1D_REPL",
"The number of lines brought into L1 data cache."},
126 {
"L1D_SPLIT.LOADS",
"The number of load operations that span two cache lines."},
127 {
"L1D_SPLIT.STORES",
"The number of store operations that span two cache lines."},
128 {
"L1I_MISSES",
"The number of instruction fetch unit misses."},
129 {
"L1I_READS",
"The number of instruction fetches."},
130 {
"L2_ADS",
"The number of cycles that the L2 address bus is in use."},
131 {
"L2_DBUS_BUSY_RD",
"The number of cycles during which the L2 data bus is busy transferring data to the core."},
132 {
"L2_IFETCH",
"The number of instruction cache line requests from the instruction fetch unit."},
133 {
"L2_LD",
"The number of L2 cache read requests from L1 cache and L2 prefetchers."},
134 {
"L2_LINES_IN",
"The number of cache lines allocated in L2 cache."},
135 {
"L2_LINES_OUT",
"The number of L2 cache lines evicted."},
136 {
"L2_LOCK",
"The number of locked accesses to cache lines that miss L1 data cache."},
137 {
"L2_M_LINES_IN",
"The number of L2 cache line modifications."},
138 {
"L2_M_LINES_OUT",
"The number of modified lines evicted from L2 cache."},
139 {
"L2_NO_REQ",
"Number of cycles during which no L2 cache requests were pending from a core."},
140 {
"L2_REJECT_BUSQ",
"Number of L2 cache requests that were rejected."},
141 {
"L2_RQSTS",
"The number of completed L2 cache requests."},
142 {
"L2_RQSTS.SELF.DEMAND.I_STATE",
"The number of completed L2 cache demand requests from this core that missed the L2 cache. This is an architectural performance event."},
143 {
"L2_RQSTS.SELF.DEMAND.MESI",
"The number of completed L2 cache demand requests from this core. This is an architectural performance event."},
144 {
"L2_ST",
"The number of store operations that miss the L1 cache and request data from the L2 cache."},
145 {
"LOAD_BLOCK.L1D",
"The number of loads blocked by the L1 data cache."},
146 {
"LOAD_BLOCK.OVERLAP_STORE",
"The number of loads that partially overlap an earlier store or are aliased with a previous store."},
147 {
"LOAD_BLOCK.STA",
"The number of loads blocked by preceding stores whose address is yet to be calculated."},
148 {
"LOAD_BLOCK.STD",
"The number of loads blocked by preceding stores to the same address whose data value is not known."},
149 {
"LOAD_BLOCK.UNTIL_RETIRE",
"The numer of load operations that were blocked until retirement."},
150 {
"LOAD_HIT_PRE",
"The number of load operations that conflicted with an prefetch to the same cache line."},
151 {
"MACHINE_NUKES.MEM_ORDER",
"The number of times the execution pipeline was restarted due to a memory ordering conflict or memory disambiguation misprediction."},
152 {
"MACHINE_NUKES.SMC",
"The number of times a program writes to a code section."},
153 {
"MACRO_INSTS.CISC_DECODED",
"The number of complex instructions decoded."},
154 {
"MACRO_INSTS.DECODED",
"The number of instructions decoded."},
155 {
"MEMORY_DISAMBIGUATION.RESET",
"The number of cycles during which memory disambiguation misprediction occurs."},
156 {
"MEMORY_DISAMBIGUATION.SUCCESS",
"The number of load operations that were successfully disambiguated."},
157 {
"MEM_LOAD_RETIRED.DTLB_MISS",
"The number of retired loads that missed the DTLB."},
158 {
"MEM_LOAD_RETIRED.L1D_LINE_MISS",
"The number of retired load operations that missed L1 data cache and that sent a request to L2 cache. This event is only available on PMC0."},
159 {
"MEM_LOAD_RETIRED.L1D_MISS",
"The number of retired load operations that missed L1 data cache. This event is only available on PMC0."},
160 {
"MEM_LOAD_RETIRED.L2_LINE_MISS",
"The number of load operations that missed L2 cache and that caused a bus request."},
161 {
"MEM_LOAD_RETIRED.L2_MISS",
"The number of load operations that missed L2 cache."},
162 {
"MUL",
"The number of multiply operations executed (only available on PMC1.)"},
163 {
"PAGE_WALKS.COUNT",
"The number of page walks executed due to an ITLB or DTLB miss."},
164 {
"PAGE_WALKS.CYCLES",
"The number of cycles spent in a page walk caused by an ITLB or DTLB miss."},
165 {
"PREF_RQSTS_DN",
"The number of downward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
166 {
"PREF_RQSTS_UP",
"The number of upward prefetches issued from the Data Prefetch Logic unit to L2 cache."},
167 {
"RAT_STALLS.ANY",
"The number of stall cycles due to any of RAT_STALLS.FLAGS RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and RAT_STALLS.ROB_READ_PORT."},
168 {
"RAT_STALLS.FLAGS",
"The number of cycles execution stalled due to a flag register induced stall."},
169 {
"RAT_STALLS.FPSW",
"The number of times the floating point status word was written."},
170 {
"RAT_STALLS.PARTIAL_CYCLES",
"The number of cycles of added instruction execution latency due to the use of a register that was partially written by previous instructions."},
171 {
"RAT_STALLS.ROB_READ_PORT",
"The number of cycles when ROB read port stalls occurred."},
172 {
"RESOURCE_STALLS.ANY",
"The number of cycles during which any resource related stall occurred."},
173 {
"RESOURCE_STALLS.BR_MISS_CLEAR",
"The number of cycles stalled due to branch misprediction."},
174 {
"RESOURCE_STALLS.FPCW",
"The number of cycles stalled due to writing the floating point control word."},
175 {
"RESOURCE_STALLS.LD_ST",
"The number of cycles during which the number of loads and stores in the pipeline exceeded their limits."},
176 {
"RESOURCE_STALLS.ROB_FULL",
"The number of cycles when the reorder buffer was full."},
177 {
"RESOURCE_STALLS.RS_FULL",
"The number of cycles during which the RS was full."},
178 {
"RS_UOPS_DISPATCHED",
"The number of micro-ops dispatched for execution."},
179 {
"RS_UOPS_DISPATCHED.PORT0",
"The number of cycles micro-ops were dispatched for execution on port 0."},
180 {
"RS_UOPS_DISPATCHED.PORT1",
"The number of cycles micro-ops were dispatched for execution on port 1."},
181 {
"RS_UOPS_DISPATCHED.PORT2",
"The number of cycles micro-ops were dispatched for execution on port 2."},
182 {
"RS_UOPS_DISPATCHED.PORT3",
"The number of cycles micro-ops were dispatched for execution on port 3."},
183 {
"RS_UOPS_DISPATCHED.PORT4",
"The number of cycles micro-ops were dispatched for execution on port 4."},
184 {
"RS_UOPS_DISPATCHED.PORT5",
"The number of cycles micro-ops were dispatched for execution on port 5."},
185 {
"SB_DRAIN_CYCLES",
"The number of cycles while the store buffer is draining."},
186 {
"SEGMENT_REG_LOADS",
"The number of segment register loads."},
187 {
"SEG_REG_RENAMES.ANY",
"The number of times the any segment register was renamed."},
188 {
"SEG_REG_RENAMES.DS",
"The number of times the ds register is renamed."},
189 {
"SEG_REG_RENAMES.ES",
"The number of times the es register is renamed."},
190 {
"SEG_REG_RENAMES.FS",
"The number of times the fs register is renamed."},
191 {
"SEG_REG_RENAMES.GS",
"The number of times the gs register is renamed."},
192 {
"SEG_RENAME_STALLS.ANY",
"The number of stalls due to lack of resource to rename any segment register."},
193 {
"SEG_RENAME_STALLS.DS",
"The number of stalls due to lack of renaming resources for the ds register."},
194 {
"SEG_RENAME_STALLS.ES",
"The number of stalls due to lack of renaming resources for the es register."},
195 {
"SEG_RENAME_STALLS.FS",
"The number of stalls due to lack of renaming resources for the fs register."},
196 {
"SEG_RENAME_STALLS.GS",
"The number of stalls due to lack of renaming resources for the gs register."},
197 {
"SIMD_ASSIST",
"The number SIMD assists invoked."},
198 {
"SIMD_COMP_INST_RETIRED.PACKED_DOUBLE",
"Then number of computational SSE2 packed double precision instructions retired."},
199 {
"SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"Then number of computational SSE2 packed single precision instructions retired."},
200 {
"SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
"Then number of computational SSE2 scalar double precision instructions retired."},
201 {
"SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
"Then number of computational SSE2 scalar single precision instructions retired."},
202 {
"SIMD_INSTR_RETIRED",
"The number of retired SIMD instructions that use MMX registers."},
203 {
"SIMD_INST_RETIRED.ANY",
"The number of streaming SIMD instructions retired."},
204 {
"SIMD_INST_RETIRED.PACKED_DOUBLE",
"The number of SSE2 packed double precision instructions retired."},
205 {
"SIMD_INST_RETIRED.PACKED_SINGLE",
"The number of SSE packed single precision instructions retired."},
206 {
"SIMD_INST_RETIRED.SCALAR_DOUBLE",
"The number of SSE2 scalar double precision instructions retired."},
207 {
"SIMD_INST_RETIRED.SCALAR_SINGLE",
"The number of SSE scalar single precision instructions retired."},
208 {
"SIMD_INST_RETIRED.VECTOR",
"The number of SSE2 vector instructions retired."},
209 {
"SIMD_SAT_INSTR_RETIRED",
"The number of saturated arithmetic SIMD instructions retired."},
210 {
"SIMD_SAT_UOP_EXEC",
"The number of SIMD saturated arithmetic micro-ops executed."},
211 {
"SIMD_UOPS_EXEC",
"The number of SIMD micro-ops executed."},
212 {
"SIMD_UOP_TYPE_EXEC.ARITHMETIC",
"The number of SIMD packed arithmetic micro-ops executed."},
213 {
"SIMD_UOP_TYPE_EXEC.LOGICAL",
"The number of SIMD packed logical micro-ops executed."},
214 {
"SIMD_UOP_TYPE_EXEC.MUL",
"The number of SIMD packed multiply micro-ops executed."},
215 {
"SIMD_UOP_TYPE_EXEC.PACK",
"The number of SIMD pack micro-ops executed."},
216 {
"SIMD_UOP_TYPE_EXEC.SHIFT",
"The number of SIMD packed shift micro-ops executed."},
217 {
"SIMD_UOP_TYPE_EXEC.UNPACK",
"The number of SIMD unpack micro-ops executed."},
218 {
"SNOOP_STALL_DRV",
"The number of times the bus stalled for snoops."},
219 {
"SSE_PRE_EXEC.L1",
"The number of PREFETCHT0 instructions executed."},
220 {
"SSE_PRE_EXEC.L2",
"The number of PREFETCHT1 instructions executed."},
221 {
"SSE_PRE_EXEC.NTA",
"The number of PREFETCHNTA instructions executed."},
222 {
"SSE_PRE_EXEC.STORES",
"The number of times SSE non-temporal store instructions were executed."},
223 {
"SSE_PRE_MISS.L1",
"The number of times the PREFETCHT0 instruction executed and missed all cache levels."},
224 {
"SSE_PRE_MISS.L2",
"The number of times the PREFETCHT1 instruction executed and missed all cache levels."},
225 {
"SSE_PRE_MISS.NTA",
"The number of times the PREFETCHNTA instruction executed and missed all cache levels."},
226 {
"STORE_BLOCK.ORDER",
"The number of cycles while a store was waiting for another store to be globally observed."},
227 {
"STORE_BLOCK.SNOOP",
"The number of cycles while a store was blocked due to a conflict with an internal or external snoop."},
228 {
"THERMAL_TRIP",
"The number of thermal trips."},
229 {
"UOPS_RETIRED.ANY",
"The number of micro-ops retired."},
230 {
"UOPS_RETIRED.FUSED",
"The number of fused micro-ops retired."},
231 {
"UOPS_RETIRED.LD_IND_BR",
"The number of micro-ops retired that fused a load with another operation."},
232 {
"UOPS_RETIRED.MACRO_FUSION",
"The number of times retired instruction pairs were fused into one micro-op."},
233 {
"UOPS_RETIRED.NON_FUSED",
"he number of non-fused micro-ops retired."},
234 {
"UOPS_RETIRED.STD_STA",
"The number of store address calculations that fused into one micro-op."},
235 {
"X87_OPS_RETIRED.ANY",
"The number of floating point computational instructions retired."},
236 {
"X87_OPS_RETIRED.FXCH",
"The number of FXCH instructions retired."},
Native_Event_LabelDescription_t Core2Processor_info[]