29 {
"BAClears",
"The number of BAClear conditions asserted."},
30 {
"BTB_Misses",
"The number of branches for which the branch table buffer did not produce a prediction."},
31 {
"Br_BAC_Missp_Exec",
"The number of branch instructions executed that were mispredicted at the front end."},
32 {
"Br_Bogus",
"The number of bogus branches."},
33 {
"Br_Call_Exec",
"The number of CALL instructions executed."},
34 {
"Br_Call_Missp_Exec",
"The number of CALL instructions executed that were mispredicted."},
35 {
"Br_Cnd_Exec",
"The number of conditional branch instructions executed."},
36 {
"Br_Cnd_Missp_Exec",
"The number of conditional branch instructions executed that were mispredicted."},
37 {
"Br_Ind_Call_Exec",
"The number of indirect CALL instructions executed."},
38 {
"Br_Ind_Exec",
"The number of indirect branches executed."},
39 {
"Br_Ind_Missp_Exec",
"The number of indirect branch instructions executed that were mispredicted."},
40 {
"Br_Inst_Exec",
"The number of branch instructions executed including speculative branches."},
41 {
"Br_Instr_Decoded",
"The number of branch instructions decoded."},
42 {
"Br_Instr_Ret",
"The number of branch instructions retired. This is an architectural performance event."},
43 {
"Br_MisPred_Ret",
"The number of mispredicted branch instructions retired. This is an architectural performance event."},
44 {
"Br_MisPred_Taken_Ret",
"The number of taken and mispredicted branches retired."},
45 {
"Br_Missp_Exec",
"The number of branch instructions executed and mispredicted at execution including branches that were not predicted."},
46 {
"Br_Ret_BAC_Missp_Exec",
"The number of return branch instructions that were mispredicted at the front end."},
47 {
"Br_Ret_Exec",
"The number of return branch instructions executed."},
48 {
"Br_Ret_Missp_Exec",
"The number of return branch instructions executed that were mispredicted."},
49 {
"Br_Taken_Ret",
"The number of taken branches retired."},
50 {
"Bus_BNR_Clocks",
"was asserted."},
51 {
"Bus_DRDY_Clocks",
"The number of external bus cycles while DRDY was asserted."},
52 {
"Bus_Data_Rcv",
"The number of cycles during which the processor is busy receiving data."},
53 {
"Bus_Locks_Clocks",
"The number of external bus cycles while the bus lock signal was asserted."},
54 {
"Bus_Not_In_Use",
"The number of cycles when there is no transaction from the core."},
55 {
"Bus_Req_Outstanding",
"The weighted cycles of cacheable bus data read requests from the data cache unit or hardware prefetcher."},
56 {
"Bus_Snoop_Stall",
"The number bus cycles while a bus snoop is stalled."},
57 {
"Bus_Snoops",
"The number of snoop responses to bus transactions."},
58 {
"Bus_Trans_Any",
"The number of completed bus transactions."},
59 {
"Bus_Trans_Brd",
"The number of read bus transactions."},
60 {
"Bus_Trans_Burst",
"The number of completed burst transactions. Retried transactions may be counted more than once."},
61 {
"Bus_Trans_Def",
"The number of completed deferred transactions."},
62 {
"Bus_Trans_IO",
"The number of completed I/O transactions counting both reads and writes."},
63 {
"Bus_Trans_Ifetch",
"Completed instruction fetch transactions."},
64 {
"Bus_Trans_Inval",
"The number completed invalidate transactions."},
65 {
"Bus_Trans_Mem",
"The number of completed memory transactions."},
66 {
"Bus_Trans_P",
"The number of completed partial transactions."},
67 {
"Bus_Trans_Pwr",
"The number of completed partial write transactions."},
68 {
"Bus_Trans_RFO",
"The number of completed read-for-ownership transactions."},
69 {
"Bus_Trans_WB",
"The number of completed writeback transactions from the data cache unit, excluding L2 writebacks."},
70 {
"Cycles_Div_Busy",
"The number of cycles the divider is busy. The event is only available on PMC0."},
71 {
"Cycles_Int_Masked",
"The number of cycles while interrupts were disabled."},
72 {
"Cycles_Int_Pending_Masked",
"The number of cycles while interrupts were disabled and interrupts were pending."},
73 {
"DCU_Snoop_To_Share",
"The number of data cache unit snoops to L1 cache lines in the shared state."},
74 {
"DCache_Cache_Lock",
"The number of cacheable locked read operations to invalid state."},
75 {
"DCache_Cache_LD",
"The number of cacheable L1 data read operations."},
76 {
"DCache_Cache_ST",
"The number cacheable L1 data write operations."},
77 {
"DCache_M_Evict",
"The number of M state data cache lines that were evicted."},
78 {
"DCache_M_Repl",
"The number of M state data cache lines that were allocated."},
79 {
"DCache_Pend_Miss",
"The weighted cycles an L1 miss was outstanding."},
80 {
"DCache_Repl",
"The number of data cache line replacements."},
81 {
"Data_Mem_Cache_Ref",
"The number of cacheable read and write operations to L1 data cache."},
82 {
"Data_Mem_Ref",
"The number of L1 data reads and writes, both cacheable and uncacheable."},
83 {
"Dbus_Busy",
"The number of core cycles during which the data bus was busy."},
84 {
"Dbus_Busy_Rd",
"The nunber of cycles during which the data bus was busy transferring data to a core."},
85 {
"Div",
"The number of divide operations including speculative operations for integer and floating point divides. This event can only be counted on PMC1."},
86 {
"Dtlb_Miss",
"The number of data references that missed the TLB."},
87 {
"ESP_Uops",
"The number of ESP folding instructions decoded."},
88 {
"EST_Trans",
"Count the number of Intel Enhanced SpeedStep transitions."},
89 {
"FP_Assist",
"The number of floating point operations that required microcode assists. The event is only available on PMC1."},
90 {
"FP_Comp_Instr_Ret",
"The number of X87 floating point compute instructions retired. The event is only available on PMC0."},
91 {
"FP_Comps_Op_Exe",
"The number of floating point computational instructions executed."},
92 {
"FP_MMX_Trans",
"The number of transitions from X87 to MMX."},
93 {
"Fused_Ld_Uops_Ret",
"The number of fused load uops retired."},
94 {
"Fused_St_Uops_Ret",
"The number of fused store uops retired."},
95 {
"Fused_Uops_Ret",
"The number of fused uops retired."},
96 {
"HW_Int_Rx",
"The number of hardware interrupts received."},
97 {
"ICache_Misses",
"The number of instruction fetch misses in the instruction cache and streaming buffers."},
98 {
"ICache_Reads",
"The number of instruction fetches from the the instruction cache and streaming buffers counting both cacheable and uncacheable fetches."},
99 {
"IFU_Mem_Stall",
"The number of cycles the instruction fetch unit was stalled while waiting for data from memory."},
100 {
"ILD_Stall",
"The number of instruction length decoder stalls."},
101 {
"ITLB_Misses",
"The number of instruction TLB misses."},
102 {
"Instr_Decoded",
"The number of instructions decoded."},
103 {
"Instr_Ret",
"The number of instructions retired. This is an architectural performance event."},
104 {
"L1_Pref_Req",
"The number of L1 prefetch request due to data cache misses."},
105 {
"L2_ADS",
"The number of L2 address strobes."},
106 {
"L2_IFetch",
"The number of instruction fetches by the instruction fetch unit from L2 cache including speculative fetches."},
107 {
"L2_LD",
"The number of L2 cache reads."},
108 {
"L2_Lines_In",
"The number of L2 cache lines allocated."},
109 {
"L2_Lines_Out",
"The number of L2 cache lines evicted."},
110 {
"L2_M_Lines_In",
"The number of L2 M state cache lines allocated."},
111 {
"L2_M_Lines_Out",
"The number of L2 M state cache lines evicted."},
112 {
"L2_No_Request_Cycles",
"The number of cycles there was no request to access L2 cache."},
113 {
"L2_Reject_Cycles",
"The number of cycles the L2 cache was busy and rejecting new requests."},
114 {
"L2_Rqsts",
"The number of L2 cache requests."},
115 {
"L2_ST",
"The number of L2 cache writes including speculative writes."},
116 {
"LD_Blocks",
"The number of load operations delayed due to store buffer blocks."},
117 {
"LLC_Misses",
"The number of cache misses for references to the last level cache, excluding misses due to hardware prefetches. This is an architectural performance event."},
118 {
"LLC_Reference",
"The number of references to the last level cache, excluding those due to hardware prefetches. This is an architectural performance event."},
119 {
"MMX_Assist",
"The number of EMMX instructions executed."},
120 {
"MMX_FP_Trans",
"The number of transitions from MMX to X87."},
121 {
"MMX_Instr_Exec",
"The number of MMX instructions executed excluding MOVQ and MOVD stores."},
122 {
"MMX_Instr_Ret",
"The number of MMX instructions retired."},
123 {
"Misalign_Mem_Ref",
"The number of misaligned data memory references, counting loads and stores."},
124 {
"Mul",
"The number of multiply operations include speculative floating point and integer multiplies. This event is available on PMC1 only."},
125 {
"NonHlt_Ref_Cycles",
"The number of non-halted bus cycles. This is an architectural performance event."},
126 {
"Pref_Rqsts_Dn",
"The number of hardware prefetch requests issued in backward streams."},
127 {
"Pref_Rqsts_Up",
"The number of hardware prefetch requests issued in forward streams."},
128 {
"Resource_Stall",
"The number of cycles where there is a resource related stall."},
129 {
"SD_Drains",
"The number of cycles while draining store buffers."},
130 {
"SIMD_FP_DP_P_Ret",
"The number of SSE/SSE2 packed double precision instructions retired."},
131 {
"SIMD_FP_DP_P_Comp_Ret",
"The number of SSE/SSE2 packed double precision compute instructions retired."},
132 {
"SIMD_FP_DP_S_Ret",
"The number of SSE/SSE2 scalar double precision instructions retired."},
133 {
"SIMD_FP_DP_S_Comp_Ret",
"The number of SSE/SSE2 scalar double precision compute instructions retired."},
134 {
"SIMD_FP_SP_P_Comp_Ret",
"The number of SSE/SSE2 packed single precision compute instructions retired."},
135 {
"SIMD_FP_SP_Ret",
"The number of SSE/SSE2 scalar single precision instructions retired, both packed and scalar."},
136 {
"SIMD_FP_SP_S_Ret",
"The number of SSE/SSE2 scalar single precision instructions retired."},
137 {
"SIMD_FP_SP_S_Comp_Ret",
"The number of SSE/SSE2 single precision compute instructions retired."},
138 {
"SIMD_Int_128_Ret",
"The number of SSE2 128-bit integer instructions retired."},
139 {
"SIMD_Int_Pari_Exec",
"The number of SIMD integer packed arithmetic instructions executed."},
140 {
"SIMD_Int_Pck_Exec",
"The number of SIMD integer pack operations instructions executed."},
141 {
"SIMD_Int_Plog_Exec",
"The number of SIMD integer packed logical instructions executed."},
142 {
"SIMD_Int_Pmul_Exec",
"The number of SIMD integer packed multiply instructions executed."},
143 {
"SIMD_Int_Psft_Exec",
"The number of SIMD integer packed shift instructions executed."},
144 {
"SIMD_Int_Sat_Exec",
"The number of SIMD integer saturating instructions executed."},
145 {
"SIMD_Int_Upck_Exec",
"The number of SIMD integer unpack instructions executed."},
146 {
"SMC_Detected",
"The number of times self-modifying code was detected."},
147 {
"SSE_NTStores_Miss",
"The number of times an SSE streaming store instruction missed all caches."},
148 {
"SSE_NTStores_Ret",
"The number of SSE streaming store instructions executed."},
149 {
"SSE_PrefNta_Miss",
"The number of times PREFETCHNTA missed all caches."},
150 {
"SSE_PrefNta_Ret",
"The number of PREFETCHNTA instructions retired."},
151 {
"SSE_PrefT1_Miss",
"The number of times PREFETCHT1 missed all caches."},
152 {
"SSE_PrefT1_Ret",
"The number of PREFETCHT1 instructions retired."},
153 {
"SSE_PrefT2_Miss",
"The number of times PREFETCHNT2 missed all caches."},
154 {
"SSE_PrefT2_Ret",
"The number of PREFETCHT2 instructions retired."},
155 {
"Seg_Reg_Loads",
"The number of segment register loads."},
156 {
"Serial_Execution_Cycles",
"The number of non-halted bus cycles of this code while the other core was halted."},
157 {
"Thermal_Trip",
"The duration in a thermal trip based on the current core clock."},
158 {
"Unfusion",
"The number of unfusion events."},
159 {
"Unhalted_Core_Cycles",
"The number of core clock cycles when the clock signal on a specific core is not halted. This is an architectural performance event."},
160 {
"Uops_Ret",
"The number of micro-ops retired."},
Native_Event_LabelDescription_t CoreProcessor_info[]