00001 /****************************/ 00002 /* THIS IS OPEN SOURCE CODE */ 00003 /****************************/ 00004 00005 /* 00006 * File: map-core.c 00007 * Author: Harald Servat 00008 * redcrash@gmail.com 00009 */ 00010 00011 #include "freebsd.h" 00012 #include "papiStdEventDefs.h" 00013 #include "map.h" 00014 00015 /**************************************************************************** 00016 CORE SUBSTRATE 00017 CORE SUBSTRATE 00018 CORE SUBSTRATE 00019 CORE SUBSTRATE 00020 CORE SUBSTRATE 00021 ****************************************************************************/ 00022 00023 /* 00024 NativeEvent_Value_CoreProcessor must match CoreProcessor_info 00025 */ 00026 00027 Native_Event_LabelDescription_t CoreProcessor_info[] = 00028 { 00029 {"BAClears", "The number of BAClear conditions asserted."}, 00030 {"BTB_Misses", "The number of branches for which the branch table buffer did not produce a prediction."}, 00031 {"Br_BAC_Missp_Exec", "The number of branch instructions executed that were mispredicted at the front end."}, 00032 {"Br_Bogus", "The number of bogus branches."}, 00033 {"Br_Call_Exec", "The number of CALL instructions executed."}, 00034 {"Br_Call_Missp_Exec", "The number of CALL instructions executed that were mispredicted."}, 00035 {"Br_Cnd_Exec", "The number of conditional branch instructions executed."}, 00036 {"Br_Cnd_Missp_Exec", "The number of conditional branch instructions executed that were mispredicted."}, 00037 {"Br_Ind_Call_Exec", "The number of indirect CALL instructions executed."}, 00038 {"Br_Ind_Exec", "The number of indirect branches executed."}, 00039 {"Br_Ind_Missp_Exec", "The number of indirect branch instructions executed that were mispredicted."}, 00040 {"Br_Inst_Exec", "The number of branch instructions executed including speculative branches."}, 00041 {"Br_Instr_Decoded", "The number of branch instructions decoded."}, 00042 {"Br_Instr_Ret", "The number of branch instructions retired. This is an architectural performance event."}, 00043 {"Br_MisPred_Ret", "The number of mispredicted branch instructions retired. This is an architectural performance event."}, 00044 {"Br_MisPred_Taken_Ret", "The number of taken and mispredicted branches retired."}, 00045 {"Br_Missp_Exec", "The number of branch instructions executed and mispredicted at execution including branches that were not predicted."}, 00046 {"Br_Ret_BAC_Missp_Exec", "The number of return branch instructions that were mispredicted at the front end."}, 00047 {"Br_Ret_Exec", "The number of return branch instructions executed."}, 00048 {"Br_Ret_Missp_Exec", "The number of return branch instructions executed that were mispredicted."}, 00049 {"Br_Taken_Ret", "The number of taken branches retired."}, 00050 {"Bus_BNR_Clocks", "was asserted."}, 00051 {"Bus_DRDY_Clocks", "The number of external bus cycles while DRDY was asserted."}, 00052 {"Bus_Data_Rcv", "The number of cycles during which the processor is busy receiving data."}, 00053 {"Bus_Locks_Clocks", "The number of external bus cycles while the bus lock signal was asserted."}, 00054 {"Bus_Not_In_Use", "The number of cycles when there is no transaction from the core."}, 00055 {"Bus_Req_Outstanding", "The weighted cycles of cacheable bus data read requests from the data cache unit or hardware prefetcher."}, 00056 {"Bus_Snoop_Stall", "The number bus cycles while a bus snoop is stalled."}, 00057 {"Bus_Snoops", "The number of snoop responses to bus transactions."}, 00058 {"Bus_Trans_Any", "The number of completed bus transactions."}, 00059 {"Bus_Trans_Brd", "The number of read bus transactions."}, 00060 {"Bus_Trans_Burst", "The number of completed burst transactions. Retried transactions may be counted more than once."}, 00061 {"Bus_Trans_Def", "The number of completed deferred transactions."}, 00062 {"Bus_Trans_IO", "The number of completed I/O transactions counting both reads and writes."}, 00063 {"Bus_Trans_Ifetch", "Completed instruction fetch transactions."}, 00064 {"Bus_Trans_Inval", "The number completed invalidate transactions."}, 00065 {"Bus_Trans_Mem", "The number of completed memory transactions."}, 00066 {"Bus_Trans_P", "The number of completed partial transactions."}, 00067 {"Bus_Trans_Pwr", "The number of completed partial write transactions."}, 00068 {"Bus_Trans_RFO", "The number of completed read-for-ownership transactions."}, 00069 {"Bus_Trans_WB", "The number of completed writeback transactions from the data cache unit, excluding L2 writebacks."}, 00070 {"Cycles_Div_Busy", "The number of cycles the divider is busy. The event is only available on PMC0."}, 00071 {"Cycles_Int_Masked", "The number of cycles while interrupts were disabled."}, 00072 {"Cycles_Int_Pending_Masked", "The number of cycles while interrupts were disabled and interrupts were pending."}, 00073 {"DCU_Snoop_To_Share", "The number of data cache unit snoops to L1 cache lines in the shared state."}, 00074 {"DCache_Cache_Lock", "The number of cacheable locked read operations to invalid state."}, 00075 {"DCache_Cache_LD", "The number of cacheable L1 data read operations."}, 00076 {"DCache_Cache_ST", "The number cacheable L1 data write operations."}, 00077 {"DCache_M_Evict", "The number of M state data cache lines that were evicted."}, 00078 {"DCache_M_Repl", "The number of M state data cache lines that were allocated."}, 00079 {"DCache_Pend_Miss", "The weighted cycles an L1 miss was outstanding."}, 00080 {"DCache_Repl", "The number of data cache line replacements."}, 00081 {"Data_Mem_Cache_Ref", "The number of cacheable read and write operations to L1 data cache."}, 00082 {"Data_Mem_Ref", "The number of L1 data reads and writes, both cacheable and uncacheable."}, 00083 {"Dbus_Busy", "The number of core cycles during which the data bus was busy."}, 00084 {"Dbus_Busy_Rd", "The nunber of cycles during which the data bus was busy transferring data to a core."}, 00085 {"Div", "The number of divide operations including speculative operations for integer and floating point divides. This event can only be counted on PMC1."}, 00086 {"Dtlb_Miss", "The number of data references that missed the TLB."}, 00087 {"ESP_Uops", "The number of ESP folding instructions decoded."}, 00088 {"EST_Trans", "Count the number of Intel Enhanced SpeedStep transitions."}, 00089 {"FP_Assist", "The number of floating point operations that required microcode assists. The event is only available on PMC1."}, 00090 {"FP_Comp_Instr_Ret", "The number of X87 floating point compute instructions retired. The event is only available on PMC0."}, 00091 {"FP_Comps_Op_Exe", "The number of floating point computational instructions executed."}, 00092 {"FP_MMX_Trans", "The number of transitions from X87 to MMX."}, 00093 {"Fused_Ld_Uops_Ret", "The number of fused load uops retired."}, 00094 {"Fused_St_Uops_Ret", "The number of fused store uops retired."}, 00095 {"Fused_Uops_Ret", "The number of fused uops retired."}, 00096 {"HW_Int_Rx", "The number of hardware interrupts received."}, 00097 {"ICache_Misses", "The number of instruction fetch misses in the instruction cache and streaming buffers."}, 00098 {"ICache_Reads", "The number of instruction fetches from the the instruction cache and streaming buffers counting both cacheable and uncacheable fetches."}, 00099 {"IFU_Mem_Stall", "The number of cycles the instruction fetch unit was stalled while waiting for data from memory."}, 00100 {"ILD_Stall", "The number of instruction length decoder stalls."}, 00101 {"ITLB_Misses", "The number of instruction TLB misses."}, 00102 {"Instr_Decoded", "The number of instructions decoded."}, 00103 {"Instr_Ret", "The number of instructions retired. This is an architectural performance event."}, 00104 {"L1_Pref_Req", "The number of L1 prefetch request due to data cache misses."}, 00105 {"L2_ADS", "The number of L2 address strobes."}, 00106 {"L2_IFetch", "The number of instruction fetches by the instruction fetch unit from L2 cache including speculative fetches."}, 00107 {"L2_LD", "The number of L2 cache reads."}, 00108 {"L2_Lines_In", "The number of L2 cache lines allocated."}, 00109 {"L2_Lines_Out", "The number of L2 cache lines evicted."}, 00110 {"L2_M_Lines_In", "The number of L2 M state cache lines allocated."}, 00111 {"L2_M_Lines_Out", "The number of L2 M state cache lines evicted."}, 00112 {"L2_No_Request_Cycles", "The number of cycles there was no request to access L2 cache."}, 00113 {"L2_Reject_Cycles", "The number of cycles the L2 cache was busy and rejecting new requests."}, 00114 {"L2_Rqsts", "The number of L2 cache requests."}, 00115 {"L2_ST", "The number of L2 cache writes including speculative writes."}, 00116 {"LD_Blocks", "The number of load operations delayed due to store buffer blocks."}, 00117 {"LLC_Misses", "The number of cache misses for references to the last level cache, excluding misses due to hardware prefetches. This is an architectural performance event."}, 00118 {"LLC_Reference", "The number of references to the last level cache, excluding those due to hardware prefetches. This is an architectural performance event."}, 00119 {"MMX_Assist", "The number of EMMX instructions executed."}, 00120 {"MMX_FP_Trans", "The number of transitions from MMX to X87."}, 00121 {"MMX_Instr_Exec", "The number of MMX instructions executed excluding MOVQ and MOVD stores."}, 00122 {"MMX_Instr_Ret", "The number of MMX instructions retired."}, 00123 {"Misalign_Mem_Ref", "The number of misaligned data memory references, counting loads and stores."}, 00124 {"Mul", "The number of multiply operations include speculative floating point and integer multiplies. This event is available on PMC1 only."}, 00125 {"NonHlt_Ref_Cycles", "The number of non-halted bus cycles. This is an architectural performance event."}, 00126 {"Pref_Rqsts_Dn", "The number of hardware prefetch requests issued in backward streams."}, 00127 {"Pref_Rqsts_Up", "The number of hardware prefetch requests issued in forward streams."}, 00128 {"Resource_Stall", "The number of cycles where there is a resource related stall."}, 00129 {"SD_Drains", "The number of cycles while draining store buffers."}, 00130 {"SIMD_FP_DP_P_Ret", "The number of SSE/SSE2 packed double precision instructions retired."}, 00131 {"SIMD_FP_DP_P_Comp_Ret", "The number of SSE/SSE2 packed double precision compute instructions retired."}, 00132 {"SIMD_FP_DP_S_Ret", "The number of SSE/SSE2 scalar double precision instructions retired."}, 00133 {"SIMD_FP_DP_S_Comp_Ret", "The number of SSE/SSE2 scalar double precision compute instructions retired."}, 00134 {"SIMD_FP_SP_P_Comp_Ret", "The number of SSE/SSE2 packed single precision compute instructions retired."}, 00135 {"SIMD_FP_SP_Ret", "The number of SSE/SSE2 scalar single precision instructions retired, both packed and scalar."}, 00136 {"SIMD_FP_SP_S_Ret", "The number of SSE/SSE2 scalar single precision instructions retired."}, 00137 {"SIMD_FP_SP_S_Comp_Ret", "The number of SSE/SSE2 single precision compute instructions retired."}, 00138 {"SIMD_Int_128_Ret", "The number of SSE2 128-bit integer instructions retired."}, 00139 {"SIMD_Int_Pari_Exec", "The number of SIMD integer packed arithmetic instructions executed."}, 00140 {"SIMD_Int_Pck_Exec", "The number of SIMD integer pack operations instructions executed."}, 00141 {"SIMD_Int_Plog_Exec", "The number of SIMD integer packed logical instructions executed."}, 00142 {"SIMD_Int_Pmul_Exec", "The number of SIMD integer packed multiply instructions executed."}, 00143 {"SIMD_Int_Psft_Exec", "The number of SIMD integer packed shift instructions executed."}, 00144 {"SIMD_Int_Sat_Exec", "The number of SIMD integer saturating instructions executed."}, 00145 {"SIMD_Int_Upck_Exec", "The number of SIMD integer unpack instructions executed."}, 00146 {"SMC_Detected", "The number of times self-modifying code was detected."}, 00147 {"SSE_NTStores_Miss", "The number of times an SSE streaming store instruction missed all caches."}, 00148 {"SSE_NTStores_Ret", "The number of SSE streaming store instructions executed."}, 00149 {"SSE_PrefNta_Miss", "The number of times PREFETCHNTA missed all caches."}, 00150 {"SSE_PrefNta_Ret", "The number of PREFETCHNTA instructions retired."}, 00151 {"SSE_PrefT1_Miss", "The number of times PREFETCHT1 missed all caches."}, 00152 {"SSE_PrefT1_Ret", "The number of PREFETCHT1 instructions retired."}, 00153 {"SSE_PrefT2_Miss", "The number of times PREFETCHNT2 missed all caches."}, 00154 {"SSE_PrefT2_Ret", "The number of PREFETCHT2 instructions retired."}, 00155 {"Seg_Reg_Loads", "The number of segment register loads."}, 00156 {"Serial_Execution_Cycles", "The number of non-halted bus cycles of this code while the other core was halted."}, 00157 {"Thermal_Trip", "The duration in a thermal trip based on the current core clock."}, 00158 {"Unfusion", "The number of unfusion events."}, 00159 {"Unhalted_Core_Cycles", "The number of core clock cycles when the clock signal on a specific core is not halted. This is an architectural performance event."}, 00160 {"Uops_Ret", "The number of micro-ops retired."}, 00161 { NULL, NULL } 00162 }; 00163

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