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map-p6.c
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1 /****************************/
2 /* THIS IS OPEN SOURCE CODE */
3 /****************************/
4 
5 /*
6 * File: map-p6.c
7 * Author: Harald Servat
8 * redcrash@gmail.com
9 */
10 
11 #include "freebsd.h"
12 #include "papiStdEventDefs.h"
13 #include "map.h"
14 
15 
16 /****************************************************************************
17  P6 SUBSTRATE
18  P6 SUBSTRATE
19  P6 SUBSTRATE (aka Pentium Pro)
20  P6 SUBSTRATE
21  P6 SUBSTRATE
22 ****************************************************************************/
23 
24 /*
25  NativeEvent_Value_P6Processor must match P6Processor_info
26 */
27 
29 {
30  { "p6-baclears", "Count the number of times a static branch prediction was made by the branch decoder because the BTB did not have a prediction." },
31  { "p6-br-bogus", "Count the number of bogus branches." },
32  { "p6-br-inst-decoded", "Count the number of branch instructions decoded." },
33  { "p6-br-inst-retired", "Count the number of branch instructions retired." },
34  { "p6-br-miss-pred-retired", "Count the number of mispredicted branch instructions retired." },
35  { "p6-br-miss-pred-taken-ret", "Count the number of taken mispredicted branches retired." },
36  { "p6-br-taken-retired", "Count the number of taken branches retired." },
37  { "p6-btb-misses", "Count the number of branches for which the BTB did not produce a prediction. "},
38  { "p6-bus-bnr-drv", "Count the number of bus clock cycles during which this processor is driving the BNR# pin." },
39  { "p6-bus-data-rcv", "Count the number of bus clock cycles during which this processor is receiving data." },
40  { "p6-bus-drdy-clocks", "Count the number of clocks during which DRDY# is asserted." },
41  { "p6-bus-hit-drv", "Count the number of bus clock cycles during which this processor is driving the HIT# pin." },
42  { "p6-bus-hitm-drv", "Count the number of bus clock cycles during which this processor is driving the HITM# pin." },
43  { "p6-bus-lock-clocks", "Count the number of clocks during with LOCK# is asserted on the external system bus." },
44  { "p6-bus-req-outstanding", "Count the number of bus requests outstanding in any given cycle." },
45  { "p6-bus-snoop-stall", "Count the number of clock cycles during which the bus is snoop stalled." },
46  { "p6-bus-tran-any", "Count the number of completed bus transactions of any kind." },
47  { "p6-bus-tran-brd", "Count the number of burst read transactions." },
48  { "p6-bus-tran-burst", "Count the number of completed burst transactions." },
49  { "p6-bus-tran-def", "Count the number of completed deferred transactions." },
50  { "p6-bus-tran-ifetch", "Count the number of completed instruction fetch transactions." },
51  { "p6-bus-tran-inval", "Count the number of completed invalidate transactions." },
52  { "p6-bus-tran-mem", "Count the number of completed memory transactions." },
53  { "p6-bus-tran-pwr", "Count the number of completed partial write transactions." },
54  { "p6-bus-tran-rfo", "Count the number of completed read-for-ownership transactions." },
55  { "p6-bus-trans-io", "Count the number of completed I/O transactions." },
56  { "p6-bus-trans-p", "Count the number of completed partial transactions." },
57  { "p6-bus-trans-wb", "Count the number of completed write-back transactions." },
58  { "p6-cpu-clk-unhalted", "Count the number of cycles during with the processor was not halted." },
59  { "p6-cycles-div-busy", "Count the number of cycles during which the divider is busy and cannot accept new divides." },
60  { "p6-cycles-in-pending-and-masked", "Count the number of processor cycles for which interrupts were disabled and interrupts were pending." },
61  { "p6-cycles-int-masked", "Count the number of processor cycles for which interrupts were disabled." },
62  { "p6-data-mem-refs", "Count all loads and all stores using any memory type, including internal retries." },
63  { "p6-dcu-lines-in", "Count the total lines allocated in the data cache unit." },
64  { "p6-dcu-m-lines-in", "Count the number of M state lines allocated in the data cache unit." },
65  { "p6-dcu-m-lines-out", "Count the number of M state lines evicted from the data cache unit." },
66  { "p6-dcu-miss-outstanding", "Count the weighted number of cycles while a data cache unit miss is outstanding, incremented by the number of outstanding cache misses at any time."},
67  { "p6-div", "Count the number of integer and floating-point divides including speculative divides." },
68  { "p6-flops", "Count the number of computational floating point operations retired." },
69  { "p6-fp-assist", "Count the number of floating point exceptions handled by microcode." },
70  { "p6-fp-comps-ops-exe", "Count the number of computation floating point operations executed." },
71  { "p6-hw-int-rx", "Count the number of hardware interrupts received." },
72  { "p6-ifu-fetch", "Count the number of instruction fetches, both cacheable and non-cacheable." },
73  { "p6-ifu-fetch-miss", "Count the number of instruction fetch misses" },
74  { "p6-ifu-mem-stall", "Count the number of cycles instruction fetch is stalled for any reason." },
75  { "p6-ild-stall", "Count the number of cycles the instruction length decoder is stalled." },
76  { "p6-inst-decoded", "Count the number of instructions decoded." },
77  { "p6-inst-retired", "Count the number of instructions retired." },
78  { "p6-itlb-miss", "Count the number of instruction TLB misses." },
79  { "p6-l2-ads", "Count the number of L2 address strobes." },
80  { "p6-l2-dbus-busy", "Count the number of cycles during which the L2 cache data bus was busy." },
81  { "p6-l2-dbus-busy-rd", "Count the number of cycles during which the L2 cache data bus was busy transferring read data from L2 to the processor." },
82  { "p6-l2-ifetch", "Count the number of L2 instruction fetches." },
83  { "p6-l2-ld", "Count the number of L2 data loads." },
84  { "p6-l2-lines-in", "Count the number of L2 lines allocated." },
85  { "p6-l2-lines-out", "Count the number of L2 lines evicted." },
86  { "p6-l2-m-lines-inm", "Count the number of modified lines allocated in L2 cache." },
87  { "p6-l2-m-lines-outm", "Count the number of L2 M-state lines evicted." },
88  { "p6-l2-rqsts", "Count the total number of L2 requests." },
89  { "p6-l2-st", "Count the number of L2 data stores." },
90  { "p6-ld-blocks", "Count the number of load operations delayed due to store buffer blocks." },
91  { "p6-misalign-mem-ref", "Count the number of misaligned data memory references (crossing a 64 bit boundary)." },
92  { "p6-mul", "Count the number of floating point multiplies, including speculative multiplies." },
93  { "p6-partial-rat-stalls", "Count the number of cycles or events for partial stalls." },
94  { "p6-resource-stalls", "Count the number of cycles there was a resource related stall of any kind." },
95  { "p6-sb-drains", "Count the number of cycles the store buffer is draining." },
96  { "p6-segment-reg-loads", "Count the number of segment register loads." },
97  { "p6-uops-retired", "Count the number of micro-ops retired." },
98  { NULL, NULL }
99 };
100 
Native_Event_LabelDescription_t P6Processor_info[]
Definition: map-p6.c:28