aix-memory.c File Reference

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Functions

int _aix_get_memory_info (PAPI_hw_info_t *mem_info, int type)
int _aix_get_dmem_info (PAPI_dmem_info_t *d)

Function Documentation

int _aix_get_dmem_info ( PAPI_dmem_info_t d  ) 

Definition at line 64 of file aix-memory.c.

00065 {
00066     /* This function has been reimplemented 
00067        to conform to current interface.
00068        It has not been tested.
00069        Nor has it been confirmed for completeness.
00070        dkt 05-10-06
00071      */
00072 
00073     struct procsinfo pi;
00074     pid_t mypid = getpid(  );
00075     pid_t pid;
00076     int found = 0;
00077 
00078     pid = 0;
00079     while ( 1 ) {
00080         if ( getprocs( &pi, sizeof ( pi ), 0, 0, &pid, 1 ) != 1 )
00081             break;
00082         if ( mypid == pi.pi_pid ) {
00083             found = 1;
00084             break;
00085         }
00086     }
00087     if ( !found )
00088         return ( PAPI_ESYS );
00089 
00090     d->size = pi.pi_size;
00091     d->resident = pi.pi_drss + pi.pi_trss;
00092     d->high_water_mark = PAPI_EINVAL;
00093     d->shared = PAPI_EINVAL;
00094     d->text = pi.pi_trss;    /* this is a guess */
00095     d->library = PAPI_EINVAL;
00096     d->heap = PAPI_EINVAL;
00097     d->locked = PAPI_EINVAL;
00098     d->stack = PAPI_EINVAL;
00099     d->pagesize = getpagesize(  );
00100 
00101     return ( PAPI_OK );
00102 }

int _aix_get_memory_info ( PAPI_hw_info_t mem_info,
int  type 
)

Definition at line 16 of file aix-memory.c.

00017 {
00018     PAPI_mh_level_t *L = mem_info->mem_hierarchy.level;
00019 
00020     /* Not quite sure what bit 30 indicates.
00021        I'm assuming it flags a unified tlb */
00022     if ( _system_configuration.tlb_attrib & ( 1 << 30 ) ) {
00023         L[0].tlb[0].type = PAPI_MH_TYPE_UNIFIED;
00024         L[0].tlb[0].num_entries = _system_configuration.itlb_size;
00025         L[0].tlb[0].type = PAPI_MH_TYPE_UNIFIED;
00026     } else {
00027         L[0].tlb[0].type = PAPI_MH_TYPE_INST;
00028         L[0].tlb[0].num_entries = _system_configuration.itlb_size;
00029         L[0].tlb[0].associativity = _system_configuration.itlb_asc;
00030         L[0].tlb[1].type = PAPI_MH_TYPE_DATA;
00031         L[0].tlb[1].num_entries = _system_configuration.dtlb_size;
00032         L[0].tlb[1].associativity = _system_configuration.dtlb_asc;
00033     }
00034     /* Not quite sure what bit 30 indicates.
00035        I'm assuming it flags a unified cache */
00036     if ( _system_configuration.cache_attrib & ( 1 << 30 ) ) {
00037         L[0].cache[0].type = PAPI_MH_TYPE_UNIFIED;
00038         L[0].cache[0].size = _system_configuration.icache_size;
00039         L[0].cache[0].associativity = _system_configuration.icache_asc;
00040         L[0].cache[0].line_size = _system_configuration.icache_line;
00041     } else {
00042         L[0].cache[0].type = PAPI_MH_TYPE_INST;
00043         L[0].cache[0].size = _system_configuration.icache_size;
00044         L[0].cache[0].associativity = _system_configuration.icache_asc;
00045         L[0].cache[0].line_size = _system_configuration.icache_line;
00046         L[0].cache[1].type = PAPI_MH_TYPE_DATA;
00047         L[0].cache[1].size = _system_configuration.dcache_size;
00048         L[0].cache[1].associativity = _system_configuration.dcache_asc;
00049         L[0].cache[1].line_size = _system_configuration.dcache_line;
00050     }
00051     L[1].cache[0].type = PAPI_MH_TYPE_UNIFIED;
00052     L[1].cache[0].size = _system_configuration.L2_cache_size;
00053     L[1].cache[0].associativity = _system_configuration.L2_cache_asc;
00054     /* is there a line size for Level 2 cache? */
00055 
00056     /* it looks like we've always got at least 2 levels of info */
00057     /* what about level 3 cache? */
00058     mem_info->mem_hierarchy.levels = 2;
00059 
00060     return PAPI_OK;
00061 }


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