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perfctr-ppc64.c
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1 /****************************/
2 /* THIS IS OPEN SOURCE CODE */
3 /****************************/
4 
5 /*
6 * File: perfctr-ppc64.c
7 * Author: Maynard Johnson
8 * maynardj@us.ibm.com
9 * Mods: <your name here>
10 * <your email address>
11 */
12 
13 /* PAPI stuff */
14 #include "papi.h"
15 #include "papi_internal.h"
16 #include "papi_vector.h"
17 #include SUBSTRATE
18 
19 #ifdef PERFCTR26
20 #define PERFCTR_CPU_NAME perfctr_info_cpu_name
21 
22 #define PERFCTR_CPU_NRCTRS perfctr_info_nrctrs
23 #else
24 #define PERFCTR_CPU_NAME perfctr_cpu_name
25 #define PERFCTR_CPU_NRCTRS perfctr_cpu_nrctrs
26 #endif
27 
29 #if defined(_POWER5) || defined(_POWER5p)
30  {PAPI_L1_DCM, {DERIVED_ADD, {PNE_PM_LD_MISS_L1, PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache misses */
31  {PAPI_L1_DCA, {DERIVED_ADD, {PNE_PM_LD_REF_L1, PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache access */
32  /* can't count level 1 data cache hits due to hardware limitations. */
33  {PAPI_L1_LDM, {0, {PNE_PM_LD_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 load misses */
34  {PAPI_L1_STM, {0, {PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 store misses */
35  {PAPI_L1_DCW, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache write */
36  {PAPI_L1_DCR, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache read */
37  /* can't count level 2 data cache reads due to hardware limitations. */
38  /* can't count level 2 data cache hits due to hardware limitations. */
39  {PAPI_L2_DCM, {0, {PNE_PM_DATA_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 2 data cache misses */
40  {PAPI_L2_LDM, {0, {PNE_PM_DATA_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 2 cache read misses */
41  {PAPI_L3_DCR, {0, {PNE_PM_DATA_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 3 data cache reads */
42  /* can't count level 3 data cache hits due to hardware limitations. */
43  {PAPI_L3_DCM, {DERIVED_ADD, {PNE_PM_DATA_FROM_LMEM, PNE_PM_DATA_FROM_RMEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache misses (reads & writes) */
44  {PAPI_L3_LDM, {DERIVED_ADD, {PNE_PM_DATA_FROM_LMEM, PNE_PM_DATA_FROM_RMEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache read misses */
45  /* can't count level 1 instruction cache accesses due to hardware limitations. */
46  {PAPI_L1_ICH, {0, {PNE_PM_INST_FROM_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 1 inst cache hits */
47  /* can't count level 1 instruction cache misses due to hardware limitations. */
48  /* can't count level 2 instruction cache accesses due to hardware limitations. */
49  /* can't count level 2 instruction cache hits due to hardware limitations. */
50  {PAPI_L2_ICM, {0, {PNE_PM_INST_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 inst cache misses */
51  {PAPI_L3_ICA, {0, {PNE_PM_INST_FROM_L2MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 inst cache accesses */
52  /* can't count level 3 instruction cache hits due to hardware limitations. */
53  {PAPI_L3_ICM, {DERIVED_ADD, {PNE_PM_DATA_FROM_LMEM, PNE_PM_DATA_FROM_RMEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 instruction cache misses (reads & writes) */
54  {PAPI_FMA_INS, {0, {PNE_PM_FPU_FMA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FMA instructions completed */
55  {PAPI_TOT_IIS, {0, {PNE_PM_INST_DISP, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions issued */
56  {PAPI_TOT_INS, {0, {PNE_PM_INST_CMPL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions executed */
57  {PAPI_INT_INS, {0, {PNE_PM_FXU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Integer instructions executed */
58  {PAPI_FP_OPS, {DERIVED_ADD, {PNE_PM_FPU_1FLOP, PNE_PM_FPU_FMA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Floating point instructions executed */
59  {PAPI_FP_INS, {0, {PNE_PM_FPU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Floating point instructions executed */
60  {PAPI_TOT_CYC, {0, {PNE_PM_RUN_CYC, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Processor cycles gated by the run latch */
61  {PAPI_FDV_INS, {0, {PNE_PM_FPU_FDIV, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FD ins */
62  {PAPI_FSQ_INS, {0, {PNE_PM_FPU_FSQRT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FSq ins */
63  {PAPI_TLB_DM, {0, {PNE_PM_DTLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Data translation lookaside buffer misses */
64  {PAPI_TLB_IM, {0, {PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Instr translation lookaside buffer misses */
65  {PAPI_TLB_TL, {DERIVED_ADD, {PNE_PM_DTLB_MISS, PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total translation lookaside buffer misses */
66  {PAPI_HW_INT, {0, {PNE_PM_EXT_INT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Hardware interrupts */
67  {PAPI_STL_ICY, {0, {PNE_PM_0INST_FETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles with No Instruction Issue */
68  {PAPI_LD_INS, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load instructions */
69  {PAPI_SR_INS, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Store instructions */
70  {PAPI_LST_INS, {DERIVED_ADD, {PNE_PM_ST_REF_L1, PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load and Store instructions */
71  {PAPI_BR_INS, {0, {PNE_PM_BR_ISSUED, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch instructions */
72  {PAPI_BR_MSP, {DERIVED_ADD, {PNE_PM_BR_MPRED_CR, PNE_PM_BR_MPRED_TA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch mispredictions */
73  {PAPI_FXU_IDL, {0, {PNE_PM_FXU_IDLE, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles integer units are idle */
74  {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}} /* end of list */
75 #else
76 #ifdef _PPC970
77  {PAPI_L2_DCM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 2 data cache misses */
80  {PAPI_L2_LDM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 data cache read misses */
81  /* no PAPI_L1_ICA since PM_INST_FROM_L1 and PM_INST_FROM_L2 cannot be counted simultaneously. */
85  {PAPI_L2_ICM, {0, {PNE_PM_INST_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 2 inst cache misses */
86 #endif
87 /* Common preset events for PPC970 */
88  {PAPI_L1_DCM, {DERIVED_ADD, {PNE_PM_LD_MISS_L1, PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache misses */
89  {PAPI_L1_DCA, {DERIVED_ADD, {PNE_PM_LD_REF_L1, PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 data cache access */
90  {PAPI_FXU_IDL, {0, {PNE_PM_FXU_IDLE, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles integer units are idle */
91  {PAPI_L1_LDM, {0, {PNE_PM_LD_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 load misses */
92  {PAPI_L1_STM, {0, {PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 store misses */
93  {PAPI_L1_DCW, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache write */
94  {PAPI_L1_DCR, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Level 1 D cache read */
95  {PAPI_FMA_INS, {0, {PNE_PM_FPU_FMA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FMA instructions completed */
96  {PAPI_TOT_IIS, {0, {PNE_PM_INST_DISP, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions issued */
97  {PAPI_TOT_INS, {0, {PNE_PM_INST_CMPL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total instructions executed */
98  {PAPI_INT_INS, {0, {PNE_PM_FXU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Integer instructions executed */
99  {PAPI_FP_OPS, {DERIVED_POSTFIX, {PNE_PM_FPU0_FIN, PNE_PM_FPU1_FIN, PNE_PM_FPU_FMA, PNE_PM_FPU_STF, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, "N0|N1|+|N2|+|N3|-|"}}, /*Floating point instructions executed */
100  {PAPI_FP_INS, {0, {PNE_PM_FPU_FIN, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Floating point instructions executed */
101  {PAPI_TOT_CYC, {0, {PNE_PM_CYC, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total cycles */
102  {PAPI_FDV_INS, {0, {PNE_PM_FPU_FDIV, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FD ins */
103  {PAPI_FSQ_INS, {0, {PNE_PM_FPU_FSQRT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*FSq ins */
104  {PAPI_TLB_DM, {0, {PNE_PM_DTLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Data translation lookaside buffer misses */
105  {PAPI_TLB_IM, {0, {PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Instr translation lookaside buffer misses */
106  {PAPI_TLB_TL, {DERIVED_ADD, {PNE_PM_DTLB_MISS, PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Total translation lookaside buffer misses */
107  {PAPI_HW_INT, {0, {PNE_PM_EXT_INT, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Hardware interrupts */
108  {PAPI_STL_ICY, {0, {PNE_PM_0INST_FETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Cycles with No Instruction Issue */
109  {PAPI_LD_INS, {0, {PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load instructions */
110  {PAPI_SR_INS, {0, {PNE_PM_ST_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Store instructions */
111  {PAPI_LST_INS, {DERIVED_ADD, {PNE_PM_ST_REF_L1, PNE_PM_LD_REF_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /*Load and Store instructions */
112  {PAPI_BR_INS, {0, {PNE_PM_BR_ISSUED, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch instructions */
113  {PAPI_BR_MSP, {DERIVED_ADD, {PNE_PM_BR_MPRED_CR, PNE_PM_BR_MPRED_TA, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Branch mispredictions */
114  {PAPI_L1_DCH, {DERIVED_POSTFIX, {PNE_PM_LD_REF_L1, PNE_PM_LD_MISS_L1, PNE_PM_ST_REF_L1, PNE_PM_ST_MISS_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, "N0|N1|-|N2|+|N3|-|"}}, /* Level 1 data cache hits */
115  /* no PAPI_L2_STM, PAPI_L2_DCW nor PAPI_L2_DCA since stores/writes to L2 aren't countable */
116  {PAPI_L3_DCM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache misses (reads & writes) */
117  {PAPI_L3_LDM, {0, {PNE_PM_DATA_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 data cache read misses */
118  {PAPI_L1_ICH, {0, {PNE_PM_INST_FROM_L1, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 1 inst cache hits */
119  {PAPI_L3_ICM, {0, {PNE_PM_INST_FROM_MEM, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}}, /* Level 3 inst cache misses */
120  {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0}}} /* end of list */
121 #endif
122 };
124 
125 #if defined(_POWER5) || defined(_POWER5p)
126 unsigned long long pmc_sel_mask[NUM_COUNTER_MASKS] = {
131 };
132 #else
133 unsigned long long pmc_sel_mask[NUM_COUNTER_MASKS] = {
143 };
144 #endif
145 
146 static void
148 {
149  struct perfctr_cpu_control *cpu_ctl = &cntrl->control.cpu_control;
150  int i;
151  int num_used_counters = cpu_ctl->nractrs + cpu_ctl->nrictrs;
152  unsigned int used_counters = 0x0;
153  for ( i = 0; i < num_used_counters; i++ ) {
154  used_counters |= 1 << cpu_ctl->pmc_map[i];
155  }
156 #if defined(_POWER5) || defined(_POWER5p)
157  int freeze_pmc5_pmc6 = 0; /* for Power5 use only */
158 #endif
159 
160  for ( i = 0; i < MAX_COUNTERS; i++ ) {
161  unsigned int active_counter = ( ( 1 << i ) & used_counters );
162  if ( !active_counter ) {
163 #if defined(_POWER5) || defined(_POWER5p)
164  if ( i > 3 )
165  freeze_pmc5_pmc6++;
166  else
167  cpu_ctl->ppc64.mmcr1 &= pmc_sel_mask[i];
168 #else
169  if ( i < 2 ) {
170  cpu_ctl->ppc64.mmcr0 &= pmc_sel_mask[i];
171  } else {
172  cpu_ctl->ppc64.mmcr1 &= pmc_sel_mask[i];
173  if ( i == ( MAX_COUNTERS - 1 ) )
174  cpu_ctl->ppc64.mmcra &= pmc_sel_mask[NUM_COUNTER_MASKS - 1];
175  }
176 #endif
177  }
178  }
179 #if defined(_POWER5) || defined(_POWER5p)
180  if ( freeze_pmc5_pmc6 == 2 )
181  cpu_ctl->ppc64.mmcr0 |= PMC5_PMC6_FREEZE;
182 #endif
183 }
184 static int
185 set_domain( hwd_control_state_t * cntrl, unsigned int domain )
186 {
187  int did = 0;
188 
189  /* A bit setting of '0' indicates "count this context".
190  * Start off by turning off counting for all contexts;
191  * then, selectively re-enable.
192  */
193  cntrl->control.cpu_control.ppc64.mmcr0 |=
195  if ( domain & PAPI_DOM_USER ) {
196  cntrl->control.cpu_control.ppc64.mmcr0 |= PERF_USER;
197  cntrl->control.cpu_control.ppc64.mmcr0 ^= PERF_USER;
198  did = 1;
199  }
200  if ( domain & PAPI_DOM_KERNEL ) {
201  cntrl->control.cpu_control.ppc64.mmcr0 |= PERF_KERNEL;
202  cntrl->control.cpu_control.ppc64.mmcr0 ^= PERF_KERNEL;
203  did = 1;
204  }
205  if ( domain & PAPI_DOM_SUPERVISOR ) {
206  cntrl->control.cpu_control.ppc64.mmcr0 |= PERF_HYPERVISOR;
207  cntrl->control.cpu_control.ppc64.mmcr0 ^= PERF_HYPERVISOR;
208  did = 1;
209  }
210 
211  if ( did ) {
212  return ( PAPI_OK );
213  } else {
214  return ( PAPI_EINVAL );
215  }
216 
217 }
218 
219 
220 //extern native_event_entry_t *native_table;
221 //extern hwi_search_t _papi_hwd_preset_map[];
223 
224 #ifdef DEBUG
225 void
226 print_control( const struct perfctr_cpu_control *control )
227 {
228  unsigned int i;
229 
230  SUBDBG( "Control used:\n" );
231  SUBDBG( "tsc_on\t\t\t%u\n", control->tsc_on );
232  SUBDBG( "nractrs\t\t\t%u\n", control->nractrs );
233  SUBDBG( "nrictrs\t\t\t%u\n", control->nrictrs );
234  SUBDBG( "mmcr0\t\t\t0x%X\n", control->ppc64.mmcr0 );
235  SUBDBG( "mmcr1\t\t\t0x%llX\n",
236  ( unsigned long long ) control->ppc64.mmcr1 );
237  SUBDBG( "mmcra\t\t\t0x%X\n", control->ppc64.mmcra );
238 
239  for ( i = 0; i < ( control->nractrs + control->nrictrs ); ++i ) {
240  SUBDBG( "pmc_map[%u]\t\t%u\n", i, control->pmc_map[i] );
241  if ( control->ireset[i] ) {
242  SUBDBG( "ireset[%d]\t%X\n", i, control->ireset[i] );
243  }
244  }
245 
246 }
247 #endif
248 
249 
250 /* Assign the global native and preset table pointers, find the native
251  table's size in memory and then call the preset setup routine. */
252 int
253 setup_ppc64_presets( int cputype )
254 {
255  preset_search_map = preset_name_map_PPC64;
256  return ( _papi_hwi_setup_all_presets( preset_search_map, NULL ) );
257 }
258 
259 /*called when an EventSet is allocated */
260 int
262 {
263  int i = 0;
264  for ( i = 0; i < _papi_hwi_system_info.sub_info.num_cntrs; i++ ) {
265  ptr->control.cpu_control.pmc_map[i] = i;
266  }
267  ptr->control.cpu_control.tsc_on = 1;
268  set_domain( ptr, _papi_hwi_system_info.sub_info.default_domain );
269  return ( PAPI_OK );
270 }
271 
272 /* At init time, the higher level library should always allocate and
273  reserve EventSet zero. */
274 
275 
276 /* Called once per process. */
277 /* No longer needed if not implemented
278 int _papi_hwd_shutdown_global(void) {
279  return (PAPI_OK);
280 } */
281 
282 
283 /* this function recusively does Modified Bipartite Graph counter allocation
284  success return 1
285  fail return 0
286 */
287 static int
289 {
290  int i, j, group = -1;
291  unsigned int map[GROUP_INTS];
292 
293  for ( i = 0; i < GROUP_INTS; i++ ) {
294  map[i] = event_list[0].ra_group[i];
295  }
296 
297  for ( i = 1; i < size; i++ ) {
298  for ( j = 0; j < GROUP_INTS; j++ )
299  map[j] &= event_list[i].ra_group[j];
300  }
301 
302  for ( i = 0; i < GROUP_INTS; i++ ) {
303  if ( map[i] ) {
304  group = ffs( map[i] ) - 1 + i * 32;
305  break;
306  }
307  }
308 
309  if ( group < 0 )
310  return group; /* allocation fail */
311  else {
312  for ( i = 0; i < size; i++ ) {
313  for ( j = 0; j < MAX_COUNTERS; j++ ) {
314  if ( event_list[i].ra_counter_cmd[j] >= 0
315  && event_list[i].ra_counter_cmd[j] ==
316  group_map[group].counter_cmd[j] )
317  event_list[i].ra_position = j;
318  }
319  }
320  return group;
321  }
322 }
323 
324 
325 /* Register allocation */
326 int
328 {
329  hwd_control_state_t *this_state = &ESI->machdep;
330  int i, j, natNum, index;
331  ppc64_reg_alloc_t event_list[MAX_COUNTERS];
332  int group;
333 
334  /* not yet successfully mapped, but have enough slots for events */
335 
336  /* Initialize the local structure needed
337  for counter allocation and optimization. */
338  natNum = ESI->NativeCount;
339  for ( i = 0; i < natNum; i++ ) {
340  event_list[i].ra_position = -1;
341  for ( j = 0; j < MAX_COUNTERS; j++ ) {
342  if ( ( index =
344  ni_event & PAPI_NATIVE_AND_MASK].index ) <
345  0 )
346  return PAPI_ECNFLCT;
347  event_list[i].ra_counter_cmd[j] =
349  }
350  for ( j = 0; j < GROUP_INTS; j++ ) {
351  if ( ( index =
353  ni_event & PAPI_NATIVE_AND_MASK].index ) <
354  0 )
355  return PAPI_ECNFLCT;
356  event_list[i].ra_group[j] = native_table[index].resources.group[j];
357  }
358  }
359  if ( ( group = do_counter_allocation( event_list, natNum ) ) >= 0 ) { /* successfully mapped */
360  /* copy counter allocations info back into NativeInfoArray */
361  this_state->group_id = group;
362  for ( i = 0; i < natNum; i++ ) {
363 // ESI->NativeInfoArray[i].ni_position = event_list[i].ra_position;
364  this_state->control.cpu_control.pmc_map[i] =
365  event_list[i].ra_position;
366  ESI->NativeInfoArray[i].ni_position = i;
367  }
368  /* update the control structure based on the NativeInfoArray */
369  SUBDBG( "Group ID: %d\n", group );
370 
371  return PAPI_OK;
372  } else {
373  return PAPI_ECNFLCT;
374  }
375 }
376 
377 /* This function clears the current contents of the control structure and
378  updates it with whatever resources are allocated for all the native events
379  in the native info structure array. */
380 int
382  NativeInfo_t * native, int count,
383  hwd_context_t * context )
384 {
385 
386 
387  this_state->control.cpu_control.nractrs =
388  count - this_state->control.cpu_control.nrictrs;
389  // save control state
390  unsigned int save_mmcr0_ctlbits =
391  PERF_CONTROL_MASK & this_state->control.cpu_control.ppc64.mmcr0;
392 
393  this_state->control.cpu_control.ppc64.mmcr0 =
394  group_map[this_state->group_id].mmcr0 | save_mmcr0_ctlbits;
395 
396  unsigned long long mmcr1 =
397  ( ( unsigned long long ) group_map[this_state->group_id].mmcr1U ) << 32;
398  mmcr1 += group_map[this_state->group_id].mmcr1L;
399  this_state->control.cpu_control.ppc64.mmcr1 = mmcr1;
400 
401  this_state->control.cpu_control.ppc64.mmcra =
402  group_map[this_state->group_id].mmcra;
403 
404  clear_unused_pmcsel_bits( this_state );
405  return PAPI_OK;
406 }
407 
408 
409 int
411 {
412  int error;
413 /* clear_unused_pmcsel_bits(this_state); moved to update_control_state */
414 #ifdef DEBUG
415  print_control( &state->control.cpu_control );
416 #endif
417  if ( state->rvperfctr != NULL ) {
418  if ( ( error =
419  rvperfctr_control( state->rvperfctr, &state->control ) ) < 0 ) {
420  SUBDBG( "rvperfctr_control returns: %d\n", error );
422  return ( PAPI_ESYS );
423  }
424  return ( PAPI_OK );
425  }
426  if ( ( error = vperfctr_control( ctx->perfctr, &state->control ) ) < 0 ) {
427  SUBDBG( "vperfctr_control returns: %d\n", error );
429  return ( PAPI_ESYS );
430  }
431  return ( PAPI_OK );
432 }
433 
434 int
436 {
437  if ( state->rvperfctr != NULL ) {
438  if ( rvperfctr_stop( ( struct rvperfctr * ) ctx->perfctr ) < 0 ) {
440  return ( PAPI_ESYS );
441  }
442  return ( PAPI_OK );
443  }
444  if ( vperfctr_stop( ctx->perfctr ) < 0 ) {
446  return ( PAPI_ESYS );
447  }
448  return ( PAPI_OK );
449 }
450 
451 int
452 _papi_hwd_read( hwd_context_t * ctx, hwd_control_state_t * spc, long long **dp,
453  int flags )
454 {
455  if ( flags & PAPI_PAUSED ) {
456  vperfctr_read_state( ctx->perfctr, &spc->state, NULL );
457  } else {
458  SUBDBG( "vperfctr_read_ctrs\n" );
459  if ( spc->rvperfctr != NULL ) {
460  rvperfctr_read_ctrs( spc->rvperfctr, &spc->state );
461  } else {
462  vperfctr_read_ctrs( ctx->perfctr, &spc->state );
463  }
464  }
465 
466  *dp = ( long long * ) spc->state.pmc;
467 #ifdef DEBUG
468  {
469  if ( ISLEVEL( DEBUG_SUBSTRATE ) ) {
470  int i;
471  for ( i = 0;
472  i <
473  spc->control.cpu_control.nractrs +
474  spc->control.cpu_control.nrictrs; i++ ) {
475  SUBDBG( "raw val hardware index %d is %lld\n", i,
476  ( long long ) spc->state.pmc[i] );
477  }
478  }
479  }
480 #endif
481  return ( PAPI_OK );
482 }
483 
484 
485 int
487 {
488  return ( _papi_hwd_start( ctx, cntrl ) );
489 }
490 
491 
492 /* This routine is for shutting down threads, including the
493  master thread. */
494 int
496 {
497  int retval = vperfctr_unlink( ctx->perfctr );
498  SUBDBG( "_papi_hwd_shutdown vperfctr_unlink(%p) = %d\n", ctx->perfctr,
499  retval );
500  vperfctr_close( ctx->perfctr );
501  SUBDBG( "_papi_hwd_shutdown vperfctr_close(%p)\n", ctx->perfctr );
502  memset( ctx, 0x0, sizeof ( hwd_context_t ) );
503 
504  if ( retval )
505  return ( PAPI_ESYS );
506  return ( PAPI_OK );
507 }
508 
509 
510 /* Perfctr requires that interrupting counters appear at the end of the pmc list
511  In the case a user wants to interrupt on a counter in an evntset that is not
512  among the last events, we need to move the perfctr virtual events around to
513  make it last. This function swaps two perfctr events, and then adjust the
514  position entries in both the NativeInfoArray and the EventInfoArray to keep
515  everything consistent.
516 */
517 static void
518 swap_events( EventSetInfo_t * ESI, struct hwd_pmc_control *contr, int cntr1,
519  int cntr2 )
520 {
521  unsigned int ui;
522  int si, i, j;
523 
524  for ( i = 0; i < ESI->NativeCount; i++ ) {
525  if ( ESI->NativeInfoArray[i].ni_position == cntr1 )
526  ESI->NativeInfoArray[i].ni_position = cntr2;
527  else if ( ESI->NativeInfoArray[i].ni_position == cntr2 )
528  ESI->NativeInfoArray[i].ni_position = cntr1;
529  }
530  for ( i = 0; i < ESI->NumberOfEvents; i++ ) {
531  for ( j = 0; ESI->EventInfoArray[i].pos[j] >= 0; j++ ) {
532  if ( ESI->EventInfoArray[i].pos[j] == cntr1 )
533  ESI->EventInfoArray[i].pos[j] = cntr2;
534  else if ( ESI->EventInfoArray[i].pos[j] == cntr2 )
535  ESI->EventInfoArray[i].pos[j] = cntr1;
536  }
537  }
538  ui = contr->cpu_control.pmc_map[cntr1];
539  contr->cpu_control.pmc_map[cntr1] = contr->cpu_control.pmc_map[cntr2];
540  contr->cpu_control.pmc_map[cntr2] = ui;
541 
542  si = contr->cpu_control.ireset[cntr1];
543  contr->cpu_control.ireset[cntr1] = contr->cpu_control.ireset[cntr2];
544  contr->cpu_control.ireset[cntr2] = si;
545 }
546 
547 
548 int
549 _papi_hwd_set_overflow( EventSetInfo_t * ESI, int EventIndex, int threshold )
550 {
551  hwd_control_state_t *this_state = &ESI->machdep;
552  struct hwd_pmc_control *contr = &this_state->control;
553  int i, ncntrs, nricntrs = 0, nracntrs = 0, retval = 0;
554 
555  OVFDBG( "EventIndex=%d, threshold = %d\n", EventIndex, threshold );
556 
557  /* The correct event to overflow is EventIndex */
558  ncntrs = _papi_hwi_system_info.sub_info.num_cntrs;
559  i = ESI->EventInfoArray[EventIndex].pos[0];
560  if ( i >= ncntrs ) {
561  OVFDBG( "Selector id (%d) larger than ncntrs (%d)\n", i, ncntrs );
562  return PAPI_EINVAL;
563  }
564  if ( threshold != 0 ) { /* Set an overflow threshold */
565  if ( ESI->EventInfoArray[EventIndex].derived ) {
566  OVFDBG( "Can't overflow on a derived event.\n" );
567  return PAPI_EINVAL;
568  }
569 
570  if ( ( retval =
571  _papi_hwi_start_signal( _papi_hwi_system_info.sub_info.
572  hardware_intr_sig,
573  NEED_CONTEXT ) ) != PAPI_OK )
574  return ( retval );
575 
576  contr->cpu_control.ireset[i] = PMC_OVFL - threshold;
577  nricntrs = ++contr->cpu_control.nrictrs;
578  nracntrs = --contr->cpu_control.nractrs;
579  contr->si_signo = _papi_hwi_system_info.sub_info.hardware_intr_sig;
580  contr->cpu_control.ppc64.mmcr0 |= PERF_INT_ENABLE;
581 
582  /* move this event to the bottom part of the list if needed */
583  if ( i < nracntrs )
584  swap_events( ESI, contr, i, nracntrs );
585 
586  OVFDBG( "Modified event set\n" );
587  } else {
588  if ( contr->cpu_control.ppc64.mmcr0 & PERF_INT_ENABLE ) {
589  contr->cpu_control.ireset[i] = 0;
590  nricntrs = --contr->cpu_control.nrictrs;
591  nracntrs = ++contr->cpu_control.nractrs;
592  if ( !nricntrs )
593  contr->cpu_control.ppc64.mmcr0 &= ( ~PERF_INT_ENABLE );
594  }
595  /* move this event to the top part of the list if needed */
596  if ( i >= nracntrs )
597  swap_events( ESI, contr, i, nracntrs - 1 );
598  if ( !nricntrs )
599  contr->si_signo = 0;
600 
601  OVFDBG( "Modified event set\n" );
602 
603  retval =
604  _papi_hwi_stop_signal( _papi_hwi_system_info.sub_info.
605  hardware_intr_sig );
606  }
607 #ifdef DEBUG
608  print_control( &contr->cpu_control );
609 #endif
610  OVFDBG( "%s:%d: Hardware overflow is still experimental.\n", __FILE__,
611  __LINE__ );
612  OVFDBG( "End of call. Exit code: %d\n", retval );
613 
614  return ( retval );
615 }
616 
617 
618 
619 int
620 _papi_hwd_set_profile( EventSetInfo_t * ESI, int EventIndex, int threshold )
621 {
622  /* This function is not used and shouldn't be called. */
623  return PAPI_ECMP;
624 }
625 
626 
627 int
629 {
630  ESI->profile.overflowcount = 0;
631  return PAPI_OK;
632 }
633 
634 int
636 {
637  return set_domain( cntrl, domain );
638 }
639 
640 /* Routines to support an opaque native event table */
641 char *
642 _papi_hwd_ntv_code_to_name( unsigned int EventCode )
643 {
644  if ( ( EventCode & PAPI_NATIVE_AND_MASK ) >=
645  _papi_hwi_system_info.sub_info.num_native_events )
646  return ( '\0' ); // return a null string for invalid events
647  return ( native_name_map[EventCode & PAPI_NATIVE_AND_MASK].name );
648 }
649 
650 int
651 _papi_hwd_ntv_code_to_bits( unsigned int EventCode, hwd_register_t * bits )
652 {
653  if ( ( EventCode & PAPI_NATIVE_AND_MASK ) >=
654  _papi_hwi_system_info.sub_info.num_native_events ) {
655  return ( PAPI_ENOEVNT );
656  }
657 
658  memcpy( bits,
659  &native_table[native_name_map[EventCode & PAPI_NATIVE_AND_MASK].
660  index].resources, sizeof ( hwd_register_t ) );
661  return ( PAPI_OK );
662 }
663 
664 static void
665 copy_value( unsigned int val, char *nam, char *names, unsigned int *values,
666  int len )
667 {
668  *values = val;
669  strncpy( names, nam, len );
670  names[len - 1] = 0;
671 }
672 
673 
674 char *
675 _papi_hwd_ntv_code_to_descr( unsigned int EventCode )
676 {
677  if ( ( EventCode & PAPI_NATIVE_AND_MASK ) >=
678  _papi_hwi_system_info.sub_info.num_native_events ) {
679  return "\0";
680  }
681  return ( native_table
682  [native_name_map[EventCode & PAPI_NATIVE_AND_MASK].index].
683  description );
684 }
685 
686 int
687 _papi_hwd_ntv_enum_events( unsigned int *EventCode, int modifier )
688 {
689  if ( modifier == PAPI_ENUM_EVENTS ) {
690  int index = *EventCode & PAPI_NATIVE_AND_MASK;
691  if ( index + 1 == MAX_NATNAME_MAP_INDEX ) {
692  return ( PAPI_ENOEVNT );
693  } else {
694  *EventCode = *EventCode + 1;
695  return ( PAPI_OK );
696  }
697  } else if ( modifier == PAPI_PWR4_ENUM_GROUPS ) {
698 /* Use this modifier for all supported PPC64 processors. */
699  unsigned int group = ( *EventCode & 0x00FF0000 ) >> 16;
700  int index = *EventCode & 0x000001FF;
701  int i;
702  unsigned int tmpg;
703 
704  *EventCode = *EventCode & 0xFF00FFFF;
705  for ( i = 0; i < GROUP_INTS; i++ ) {
706  tmpg = native_table[index].resources.group[i];
707  if ( group != 0 ) {
708  while ( ( ffs( tmpg ) + i * 32 ) <= group && tmpg != 0 )
709  tmpg = tmpg ^ ( 1 << ( ffs( tmpg ) - 1 ) );
710  }
711  if ( tmpg != 0 ) {
712  group = ffs( tmpg ) + i * 32;
713  *EventCode = *EventCode | ( group << 16 );
714  return ( PAPI_OK );
715  }
716  }
717  if ( index + 1 == MAX_NATNAME_MAP_INDEX ) {
718  return ( PAPI_ENOEVNT );
719  }
720  *EventCode = *EventCode + 1;
721  return ( PAPI_OK );
722  } else
723  return ( PAPI_EINVAL );
724 }
725 
726 papi_svector_t _ppc64_vector_table[] = {
727  {( void ( * )( ) ) _papi_hwd_init_control_state,
728  VEC_PAPI_HWD_INIT_CONTROL_STATE},
729  {( void ( * )( ) ) _papi_hwd_allocate_registers,
730  VEC_PAPI_HWD_ALLOCATE_REGISTERS},
731  {( void ( * )( ) ) _papi_hwd_update_control_state,
732  VEC_PAPI_HWD_UPDATE_CONTROL_STATE},
733  {( void ( * )( ) ) _papi_hwd_start, VEC_PAPI_HWD_START},
734  {( void ( * )( ) ) _papi_hwd_stop, VEC_PAPI_HWD_STOP},
735  {( void ( * )( ) ) _papi_hwd_read, VEC_PAPI_HWD_READ},
736  {( void ( * )( ) ) _papi_hwd_reset, VEC_PAPI_HWD_RESET},
737  {( void ( * )( ) ) _papi_hwd_shutdown, VEC_PAPI_HWD_SHUTDOWN},
738  {( void ( * )( ) ) _papi_hwd_set_overflow, VEC_PAPI_HWD_SET_OVERFLOW},
739  {( void ( * )( ) ) _papi_hwd_set_profile, VEC_PAPI_HWD_SET_PROFILE},
740  {( void ( * )( ) ) _papi_hwd_stop_profiling, VEC_PAPI_HWD_STOP_PROFILING},
741  {( void ( * )( ) ) _papi_hwd_set_domain, VEC_PAPI_HWD_SET_DOMAIN},
742  {( void ( * )( ) ) *_papi_hwd_ntv_code_to_name,
743  VEC_PAPI_HWD_NTV_CODE_TO_NAME},
744  {( void ( * )( ) ) _papi_hwd_ntv_code_to_bits,
745  VEC_PAPI_HWD_NTV_CODE_TO_BITS},
746  {( void ( * )( ) ) *_papi_hwd_ntv_code_to_descr,
747  VEC_PAPI_HWD_NTV_CODE_TO_DESCR},
748  {( void ( * )( ) ) *_papi_hwd_ntv_enum_events,
749  VEC_PAPI_HWD_NTV_ENUM_EVENTS},
750  {NULL, VEC_PAPI_END}
751 };
752 
753 int
754 ppc64_setup_vector_table( papi_vectors_t * vtable )
755 {
756  int retval = PAPI_OK;
757  retval = _papi_hwi_setup_vector_table( vtable, _ppc64_vector_table );
758 }
#define PAPI_INT_INS
Definition: fpapi.h:186
#define hwd_pmc_control
Definition: perfctr-x86.h:11
#define PAPI_TLB_TL
Definition: fpapi.h:157
int _papi_hwd_ntv_enum_events(unsigned int *EventCode, int modifier)
memset(eventId, 0, size)
#define PAPI_TLB_IM
Definition: fpapi.h:156
int _papi_hwd_read(hwd_context_t *ctx, hwd_control_state_t *spc, long long **dp, int flags)
int val
Definition: libbif.c:235
#define PERF_CONTROL_MASK
Definition: perfctr-ppc64.h:59
#define PAPI_LD_INS
Definition: fpapi.h:188
PPC64_native_map_t native_name_map[PAPI_MAX_NATIVE_EVENTS]
Definition: aix.c:46
long long flags
Definition: iozone.c:12330
#define PAPI_NULL
Definition: fpapi.h:13
#define PAPI_L1_ICM
Definition: fpapi.h:136
static void clear_unused_pmcsel_bits(hwd_control_state_t *cntrl)
int _papi_hwd_shutdown(hwd_context_t *ctx)
#define PAPI_ENOEVNT
Definition: fpapi.h:112
#define PAPI_TOT_INS
Definition: fpapi.h:185
#define PAPI_PAUSED
Definition: fpapi.h:31
int ppc64_setup_vector_table(papi_vectors_t *vtable)
#define PAPI_L1_DCW
Definition: fpapi.h:205
#define PAPI_FSQ_INS
Definition: fpapi.h:235
#define MAX_COUNTERS
Definition: perfctr-x86.h:8
#define PAPI_L3_DCR
Definition: fpapi.h:204
#define PAPI_TLB_DM
Definition: fpapi.h:155
#define PAPI_L1_ICH
Definition: fpapi.h:208
#define PAPI_FMA_INS
Definition: fpapi.h:183
return PAPI_OK
Definition: linux-nvml.c:458
int count
Definition: iozone.c:22422
#define PAPI_FP_OPS
Definition: fpapi.h:237
#define PAPI_L2_DCH
Definition: fpapi.h:198
#define PAPI_LST_INS
Definition: fpapi.h:195
#define DERIVED_ADD
Definition: papi_internal.h:70
#define PAPI_DOM_KERNEL
Definition: fpapi.h:22
void
Definition: iozone.c:18627
return PAPI_EINVAL
Definition: linux-nvml.c:408
static void copy_value(unsigned int val, char *nam, char *names, unsigned int *values, int len)
char * _papi_hwd_ntv_code_to_name(unsigned int EventCode)
#define PAPI_ECNFLCT
Definition: fpapi.h:113
#define PMC8_SEL_MASK
Definition: perfctr-ppc64.h:38
Return codes and api definitions.
#define NUM_COUNTER_MASKS
Definition: perfctr-ppc64.h:29
#define PAPI_BR_INS
Definition: fpapi.h:190
#define PAPI_L1_DCR
Definition: fpapi.h:202
#define PMC8a_SEL_MASK
Definition: perfctr-ppc64.h:39
int ra_position
Definition: aix.h:98
#define PMC7_SEL_MASK
Definition: perfctr-ppc64.h:37
hwd_groups_t group_map[MAX_GROUPS]
Definition: aix.c:47
#define PAPI_FDV_INS
Definition: fpapi.h:234
int _papi_hwi_setup_all_presets(hwi_search_t *findem, int cidx)
Definition: papi_preset.c:37
int i
Definition: fileop.c:140
int _papi_hwd_reset(hwd_context_t *ctx, hwd_control_state_t *cntrl)
#define PAPI_TOT_CYC
Definition: fpapi.h:194
static int set_domain(hwd_control_state_t *cntrl, unsigned int domain)
#define PAPI_SR_INS
Definition: fpapi.h:189
int _papi_hwd_allocate_registers(EventSetInfo_t *ESI)
#define PAPI_DOM_SUPERVISOR
Definition: fpapi.h:24
native_event_entry_t native_table[PAPI_MAX_NATIVE_EVENTS]
Definition: aix.c:41
#define PAPI_L2_DCM
Definition: fpapi.h:137
char *long long size
Definition: iozone.c:12023
#define PAPI_ECMP
Definition: fpapi.h:109
#define OVFDBG(format, args...)
Definition: papi_debug.h:68
int ra_counter_cmd[MAX_COUNTERS]
Definition: aix.h:100
int _papi_hwd_ntv_code_to_bits(unsigned int EventCode, hwd_register_t *bits)
#define PAPI_L3_ICA
Definition: fpapi.h:213
#define PMC6_SEL_MASK
Definition: perfctr-ppc64.h:36
static int native
Definition: event_info.c:39
#define PMC3_SEL_MASK
Definition: perfctr-ppc64.h:33
#define PAPI_L3_DCM
Definition: fpapi.h:139
#define PMC_OVFL
Definition: perfctr-ppc64.h:55
char * _papi_hwd_ntv_code_to_descr(unsigned int EventCode)
#define SUBDBG(format, args...)
Definition: papi_debug.h:63
#define PMC1_SEL_MASK
Definition: perfctr-ppc64.h:31
long long
Definition: iozone.c:19827
void PAPIERROR(char *format,...)
int _papi_hwi_start_signal(int signal, int need_context, int cidx)
Definition: extras.c:401
int _papi_hwd_start(hwd_context_t *ctx, hwd_control_state_t *state)
#define PAPI_L3_ICM
Definition: fpapi.h:140
#define GROUP_INTS
#define PAPI_BR_MSP
Definition: fpapi.h:181
int _papi_hwd_set_domain(hwd_control_state_t *cntrl, int domain)
#define PAPI_L1_DCH
Definition: fpapi.h:197
int _papi_hwi_stop_signal(int signal)
Definition: extras.c:441
#define PERF_KERNEL
Definition: perfctr-ppc64.h:56
#define PAPI_FP_INS
Definition: fpapi.h:187
int _papi_hwd_init_control_state(hwd_control_state_t *ptr)
#define PAPI_L3_LDM
Definition: fpapi.h:149
NativeInfo_t * NativeInfoArray
#define PMC4_SEL_MASK
Definition: perfctr-ppc64.h:34
EventInfo_t * EventInfoArray
#define PAPI_HW_INT
Definition: fpapi.h:176
static int do_counter_allocation(ppc64_reg_alloc_t *event_list, int size)
#define MAX_NATNAME_MAP_INDEX
#define PAPI_ESYS
Definition: fpapi.h:108
int _papi_hwd_set_profile(EventSetInfo_t *ESI, int EventIndex, int threshold)
int threshold
hwi_search_t * preset_search_map
papi_mdi_t _papi_hwi_system_info
Definition: papi_internal.c:57
unsigned int ra_group[GROUP_INTS]
Definition: aix.h:99
int pos[PAPI_EVENTS_IN_DERIVED_EVENT]
#define PERF_INT_ENABLE
Definition: perfctr-x86.h:53
#define PAPI_TOT_IIS
Definition: fpapi.h:184
#define PAPI_MAX_PRESET_EVENTS
Definition: fpapi.h:16
#define PAPI_L2_DCR
Definition: fpapi.h:203
#define PMC5_SEL_MASK
Definition: perfctr-ppc64.h:35
#define PAPI_L1_DCM
Definition: fpapi.h:135
#define RCNTRL_ERROR
Definition: perfctr-x86.h:66
int _papi_hwd_update_control_state(hwd_control_state_t *this_state, NativeInfo_t *native, int count, hwd_context_t *context)
char * name
Definition: iozone.c:23648
#define NEED_CONTEXT
Definition: papi_internal.h:97
int _papi_hwd_stop(hwd_context_t *ctx, hwd_control_state_t *state)
static void swap_events(EventSetInfo_t *ESI, struct hwd_pmc_control *contr, int cntr1, int cntr2)
child_idents[x-1] state
Definition: iozone.c:21341
#define PERF_USER
Definition: perfctr-ppc64.h:57
#define ISLEVEL(a)
Definition: papi_debug.h:54
unsigned long long pmc_sel_mask[NUM_COUNTER_MASKS]
static hwi_search_t preset_name_map_PPC64[PAPI_MAX_PRESET_EVENTS]
Definition: perfctr-ppc64.c:28
#define PAPI_NATIVE_AND_MASK
int setup_ppc64_presets(int cputype)
#define PAPI_L1_STM
Definition: fpapi.h:159
void print_control(const struct perfctr_cpu_control *control)
Definition: perfctr-x86.c:96
#define PAPI_L2_ICM
Definition: fpapi.h:138
#define PAPI_DOM_USER
Definition: fpapi.h:21
X86_register_t resources
Definition: perfctr-x86.h:137
papi_svector_t _ppc64_vector_table[]
#define PAPI_L1_LDM
Definition: fpapi.h:158
int _papi_hwd_set_overflow(EventSetInfo_t *ESI, int EventIndex, int threshold)
EventSetProfileInfo_t profile
long j
Definition: iozone.c:19135
#define PAPI_FXU_IDL
Definition: fpapi.h:152
int _papi_hwd_stop_profiling(ThreadInfo_t *master, EventSetInfo_t *ESI)
static long long values[NUM_EVENTS]
Definition: init_fini.c:10
ssize_t retval
Definition: libasync.c:338
#define PERF_HYPERVISOR
Definition: perfctr-ppc64.h:58
#define DERIVED_POSTFIX
Definition: papi_internal.h:75
const char * names[NUM_EVENTS]
#define PAPI_L1_DCA
Definition: fpapi.h:199
#define PAPI_L2_LDM
Definition: fpapi.h:160
#define PAPI_L2_ICH
Definition: fpapi.h:209
if(gettimeofday(&tp,(struct timezone *) NULL)==-1) perror("gettimeofday")
#define PAPI_L2_ICA
Definition: fpapi.h:212
#define VCNTRL_ERROR
Definition: perfctr-x86.h:65
#define PMC2_SEL_MASK
Definition: perfctr-ppc64.h:32
#define PAPI_STL_ICY
Definition: fpapi.h:172
#define DEBUG_SUBSTRATE
Definition: papi_debug.h:27
char * ptr
Definition: iozone.c:23586