30 {
"p6-baclears",
"Count the number of times a static branch prediction was made by the branch decoder because the BTB did not have a prediction." },
31 {
"p6-br-bogus",
"Count the number of bogus branches." },
32 {
"p6-br-inst-decoded",
"Count the number of branch instructions decoded." },
33 {
"p6-br-inst-retired",
"Count the number of branch instructions retired." },
34 {
"p6-br-miss-pred-retired",
"Count the number of mispredicted branch instructions retired." },
35 {
"p6-br-miss-pred-taken-ret",
"Count the number of taken mispredicted branches retired." },
36 {
"p6-br-taken-retired",
"Count the number of taken branches retired." },
37 {
"p6-btb-misses",
"Count the number of branches for which the BTB did not produce a prediction. "},
38 {
"p6-bus-bnr-drv",
"Count the number of bus clock cycles during which this processor is driving the BNR# pin." },
39 {
"p6-bus-data-rcv",
"Count the number of bus clock cycles during which this processor is receiving data." },
40 {
"p6-bus-drdy-clocks",
"Count the number of clocks during which DRDY# is asserted." },
41 {
"p6-bus-hit-drv",
"Count the number of bus clock cycles during which this processor is driving the HIT# pin." },
42 {
"p6-bus-hitm-drv",
"Count the number of bus clock cycles during which this processor is driving the HITM# pin." },
43 {
"p6-bus-lock-clocks",
"Count the number of clocks during with LOCK# is asserted on the external system bus." },
44 {
"p6-bus-req-outstanding",
"Count the number of bus requests outstanding in any given cycle." },
45 {
"p6-bus-snoop-stall",
"Count the number of clock cycles during which the bus is snoop stalled." },
46 {
"p6-bus-tran-any",
"Count the number of completed bus transactions of any kind." },
47 {
"p6-bus-tran-brd",
"Count the number of burst read transactions." },
48 {
"p6-bus-tran-burst",
"Count the number of completed burst transactions." },
49 {
"p6-bus-tran-def",
"Count the number of completed deferred transactions." },
50 {
"p6-bus-tran-ifetch",
"Count the number of completed instruction fetch transactions." },
51 {
"p6-bus-tran-inval",
"Count the number of completed invalidate transactions." },
52 {
"p6-bus-tran-mem",
"Count the number of completed memory transactions." },
53 {
"p6-bus-tran-pwr",
"Count the number of completed partial write transactions." },
54 {
"p6-bus-tran-rfo",
"Count the number of completed read-for-ownership transactions." },
55 {
"p6-bus-trans-io",
"Count the number of completed I/O transactions." },
56 {
"p6-bus-trans-p",
"Count the number of completed partial transactions." },
57 {
"p6-bus-trans-wb",
"Count the number of completed write-back transactions." },
59 {
"p6-cpu-clk-unhalted",
"Count the number of cycles during with the processor was not halted and not in a thermal trip." },
60 {
"p6-cycles-div-busy",
"Count the number of cycles during which the divider is busy and cannot accept new divides." },
61 {
"p6-cycles-in-pending-and-masked",
"Count the number of processor cycles for which interrupts were disabled and interrupts were pending." },
62 {
"p6-cycles-int-masked",
"Count the number of processor cycles for which interrupts were disabled." },
63 {
"p6-data-mem-refs",
"Count all loads and all stores using any memory type, including internal retries." },
64 {
"p6-dcu-lines-in",
"Count the total lines allocated in the data cache unit." },
65 {
"p6-dcu-m-lines-in",
"Count the number of M state lines allocated in the data cache unit." },
66 {
"p6-dcu-m-lines-out",
"Count the number of M state lines evicted from the data cache unit." },
67 {
"p6-dcu-miss-outstanding",
"Count the weighted number of cycles while a data cache unit miss is outstanding, incremented by the number of outstanding cache misses at any time."},
68 {
"p6-div",
"Count the number of integer and floating-point divides including speculative divides." },
69 {
"p6-flops",
"Count the number of computational floating point operations retired." },
70 {
"p6-fp-assist",
"Count the number of floating point exceptions handled by microcode." },
71 {
"p6-fp-comps-ops-exe",
"Count the number of computation floating point operations executed." },
72 {
"p6-hw-int-rx",
"Count the number of hardware interrupts received." },
73 {
"p6-ifu-fetch",
"Count the number of instruction fetches, both cacheable and non-cacheable." },
74 {
"p6-ifu-fetch-miss",
"Count the number of instruction fetch misses" },
75 {
"p6-ifu-mem-stall",
"Count the number of cycles instruction fetch is stalled for any reason." },
76 {
"p6-ild-stall",
"Count the number of cycles the instruction length decoder is stalled." },
77 {
"p6-inst-decoded",
"Count the number of instructions decoded." },
78 {
"p6-inst-retired",
"Count the number of instructions retired." },
79 {
"p6-itlb-miss",
"Count the number of instruction TLB misses." },
80 {
"p6-l2-ads",
"Count the number of L2 address strobes." },
81 {
"p6-l2-dbus-busy",
"Count the number of cycles during which the L2 cache data bus was busy." },
82 {
"p6-l2-dbus-busy-rd",
"Count the number of cycles during which the L2 cache data bus was busy transferring read data from L2 to the processor." },
83 {
"p6-l2-ifetch",
"Count the number of L2 instruction fetches." },
84 {
"p6-l2-ld",
"Count the number of L2 data loads." },
85 {
"p6-l2-lines-in",
"Count the number of L2 lines allocated." },
86 {
"p6-l2-lines-out",
"Count the number of L2 lines evicted." },
87 {
"p6-l2-m-lines-inm",
"Count the number of modified lines allocated in L2 cache." },
88 {
"p6-l2-m-lines-outm",
"Count the number of L2 M-state lines evicted." },
89 {
"p6-l2-rqsts",
"Count the total number of L2 requests." },
90 {
"p6-l2-st",
"Count the number of L2 data stores." },
91 {
"p6-ld-blocks",
"Count the number of load operations delayed due to store buffer blocks." },
92 {
"p6-misalign-mem-ref",
"Count the number of misaligned data memory references (crossing a 64 bit boundary)." },
93 {
"p6-mul",
"Count the number of floating point multiplies, including speculative multiplies." },
94 {
"p6-partial-rat-stalls",
"Count the number of cycles or events for partial stalls." },
95 {
"p6-resource-stalls",
"Count the number of cycles there was a resource related stall of any kind." },
96 {
"p6-sb-drains",
"Count the number of cycles the store buffer is draining." },
97 {
"p6-segment-reg-loads",
"Count the number of segment register loads." },
98 {
"p6-uops-retired",
"Count the number of micro-ops retired."},
100 {
"p6-fp-mmx-trans",
"Count the number of transitions between MMX and floating-point instructions." },
101 {
"p6-mmx-assist",
"Count the number of MMX assists executed" },
102 {
"p6-mmx-instr-exec",
"Count the number of MMX instructions executed" },
103 {
"p6-mmx-instr-ret",
"Count the number of MMX instructions retired." },
104 {
"p6-mmx-sat-instr-exec",
"Count the number of MMX saturating instructions executed" },
105 {
"p6-mmx-uops-exec",
"Count the number of MMX micro-ops executed" },
106 {
"p6-ret-seg-renames",
"Count the number of segment register rename events retired." },
107 {
"p6-seg-rename-stalls",
"Count the number of segment register renaming stalls" },
108 {
"p6-emon-kni-comp-inst-ret",
"Count the number of SSE computational instructions retired" },
109 {
"p6-emon-kni-inst-retired",
"Count the number of SSE instructions retired." },
110 {
"p6-emon-kni-pref-dispatched",
"Count the number of SSE prefetch or weakly ordered instructions dispatched." },
111 {
"p6-emon-kni-pref-miss",
"Count the number of prefetch or weakly ordered instructions that miss all caches." },
113 {
"p6-br-bac-missp-exec",
"Count the number of branch instructions executed that where mispredicted at the Front End (BAC)." },
114 {
"p6-br-call-exec",
"Count the number of call instructions executed." },
115 {
"p6-br-call-missp-exec",
"Count the number of call instructions executed that were mispredicted." },
116 {
"p6-br-cnd-exec",
"Count the number of conditional branch instructions excuted" },
117 {
"p6-br-cnd-missp-exec",
"Count the number of conditional branch instructions executed that were mispredicted." },
118 {
"p6-br-ind-call-exec",
"Count the number of indirect call instructions executed" },
119 {
"p6-br-ind-exec",
"Count the number of indirect branch instructions executed" },
120 {
"p6-br-ind-missp-exec",
"Count the number of indirect branch instructions executed that were mispredicted." },
121 {
"p6-br-inst-exec",
"Count the number of branch instructions executed but necessarily retired." },
122 {
"p6-br-missp-exec",
"Count the number of branch instructions executed that were mispredicted at execution." },
123 {
"p6-br-ret-bac-missp-exec",
"Count the number of return instructions executed that were mispredicted at the Front End (BAC)." },
124 {
"p6-br-ret-exec",
"Count the number of return instructions executed." },
125 {
"p6-br-ret-missp-exec",
"Count the number of return instructions executed that were mispredicted at execution." },
126 {
"p6-emon-esp-uops",
"Count the total number of micro-ops." },
127 {
"p6-emon-est-trans",
"Count the number of Enhanced Intel SpeedStep transitions" },
128 {
"p6-emon-fused-uops-ret",
"Count the number of retired fused micro-ops." },
129 {
"p6-emon-pref-rqsts-dn",
"Count the number of downward prefetches issued." },
130 {
"p6-emon-pref-rqsts-up",
"Count the number of upward prefetches issued." },
131 {
"p6-emon-simd-instr-retired",
"Count the number of retired MMX instructions." },
132 {
"p6-emon-sse-sse2-comp-inst-retired",
"Count the number of computational SSE instructions retired." },
133 {
"p6-emon-sse-sse2-inst-retired",
"Count the number of SSE instructions retired." },
134 {
"p6-emon-synch-uops",
"Count the number of sync micro-ops." },
135 {
"p6-emon-thermal-trip",
"Count the duration or occurrences of thermal trips." },
136 {
"p6-emon-unfusion",
"Count the number of unfusion events in the reorder buffer." },
Native_Event_LabelDescription_t P6_M_Processor_info[]