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papiStdEventDefs.h File Reference
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Macros

#define PAPI_PRESET_MASK   ((int)0x80000000)
 
#define PAPI_NATIVE_MASK   0x40000000
 
#define PAPI_PRESET_AND_MASK   0x7FFFFFFF
 
#define PAPI_NATIVE_AND_MASK   0xBFFFFFFF /* this masks just the native bit */
 
#define PAPI_MAX_PRESET_EVENTS   128 /*The maxmimum number of preset events */
 
#define PAPI_L1_DCM   (PAPI_L1_DCM_idx | PAPI_PRESET_MASK) /*Level 1 data cache misses */
 
#define PAPI_L1_ICM   (PAPI_L1_ICM_idx | PAPI_PRESET_MASK) /*Level 1 instruction cache misses */
 
#define PAPI_L2_DCM   (PAPI_L2_DCM_idx | PAPI_PRESET_MASK) /*Level 2 data cache misses */
 
#define PAPI_L2_ICM   (PAPI_L2_ICM_idx | PAPI_PRESET_MASK) /*Level 2 instruction cache misses */
 
#define PAPI_L3_DCM   (PAPI_L3_DCM_idx | PAPI_PRESET_MASK) /*Level 3 data cache misses */
 
#define PAPI_L3_ICM   (PAPI_L3_ICM_idx | PAPI_PRESET_MASK) /*Level 3 instruction cache misses */
 
#define PAPI_L1_TCM   (PAPI_L1_TCM_idx | PAPI_PRESET_MASK) /*Level 1 total cache misses */
 
#define PAPI_L2_TCM   (PAPI_L2_TCM_idx | PAPI_PRESET_MASK) /*Level 2 total cache misses */
 
#define PAPI_L3_TCM   (PAPI_L3_TCM_idx | PAPI_PRESET_MASK) /*Level 3 total cache misses */
 
#define PAPI_CA_SNP   (PAPI_CA_SNP_idx | PAPI_PRESET_MASK) /*Snoops */
 
#define PAPI_CA_SHR   (PAPI_CA_SHR_idx | PAPI_PRESET_MASK) /*Request for shared cache line (SMP) */
 
#define PAPI_CA_CLN   (PAPI_CA_CLN_idx | PAPI_PRESET_MASK) /*Request for clean cache line (SMP) */
 
#define PAPI_CA_INV   (PAPI_CA_INV_idx | PAPI_PRESET_MASK) /*Request for cache line Invalidation (SMP) */
 
#define PAPI_CA_ITV   (PAPI_CA_ITV_idx | PAPI_PRESET_MASK) /*Request for cache line Intervention (SMP) */
 
#define PAPI_L3_LDM   (PAPI_L3_LDM_idx | PAPI_PRESET_MASK) /*Level 3 load misses */
 
#define PAPI_L3_STM   (PAPI_L3_STM_idx | PAPI_PRESET_MASK) /*Level 3 store misses */
 
#define PAPI_BRU_IDL   (PAPI_BRU_IDL_idx | PAPI_PRESET_MASK) /*Cycles branch units are idle */
 
#define PAPI_FXU_IDL   (PAPI_FXU_IDL_idx | PAPI_PRESET_MASK) /*Cycles integer units are idle */
 
#define PAPI_FPU_IDL   (PAPI_FPU_IDL_idx | PAPI_PRESET_MASK) /*Cycles floating point units are idle */
 
#define PAPI_LSU_IDL   (PAPI_LSU_IDL_idx | PAPI_PRESET_MASK) /*Cycles load/store units are idle */
 
#define PAPI_TLB_DM   (PAPI_TLB_DM_idx | PAPI_PRESET_MASK) /*Data translation lookaside buffer misses */
 
#define PAPI_TLB_IM   (PAPI_TLB_IM_idx | PAPI_PRESET_MASK) /*Instr translation lookaside buffer misses */
 
#define PAPI_TLB_TL   (PAPI_TLB_TL_idx | PAPI_PRESET_MASK) /*Total translation lookaside buffer misses */
 
#define PAPI_L1_LDM   (PAPI_L1_LDM_idx | PAPI_PRESET_MASK) /*Level 1 load misses */
 
#define PAPI_L1_STM   (PAPI_L1_STM_idx | PAPI_PRESET_MASK) /*Level 1 store misses */
 
#define PAPI_L2_LDM   (PAPI_L2_LDM_idx | PAPI_PRESET_MASK) /*Level 2 load misses */
 
#define PAPI_L2_STM   (PAPI_L2_STM_idx | PAPI_PRESET_MASK) /*Level 2 store misses */
 
#define PAPI_BTAC_M   (PAPI_BTAC_M_idx | PAPI_PRESET_MASK) /*BTAC miss */
 
#define PAPI_PRF_DM   (PAPI_PRF_DM_idx | PAPI_PRESET_MASK) /*Prefetch data instruction caused a miss */
 
#define PAPI_L3_DCH   (PAPI_L3_DCH_idx | PAPI_PRESET_MASK) /*Level 3 Data Cache Hit */
 
#define PAPI_TLB_SD   (PAPI_TLB_SD_idx | PAPI_PRESET_MASK) /*Xlation lookaside buffer shootdowns (SMP) */
 
#define PAPI_CSR_FAL   (PAPI_CSR_FAL_idx | PAPI_PRESET_MASK) /*Failed store conditional instructions */
 
#define PAPI_CSR_SUC   (PAPI_CSR_SUC_idx | PAPI_PRESET_MASK) /*Successful store conditional instructions */
 
#define PAPI_CSR_TOT   (PAPI_CSR_TOT_idx | PAPI_PRESET_MASK) /*Total store conditional instructions */
 
#define PAPI_MEM_SCY   (PAPI_MEM_SCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Access */
 
#define PAPI_MEM_RCY   (PAPI_MEM_RCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Read */
 
#define PAPI_MEM_WCY   (PAPI_MEM_WCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Write */
 
#define PAPI_STL_ICY   (PAPI_STL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Issue */
 
#define PAPI_FUL_ICY   (PAPI_FUL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Issue */
 
#define PAPI_STL_CCY   (PAPI_STL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Completion */
 
#define PAPI_FUL_CCY   (PAPI_FUL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Completion */
 
#define PAPI_HW_INT   (PAPI_HW_INT_idx | PAPI_PRESET_MASK) /*Hardware interrupts */
 
#define PAPI_BR_UCN   (PAPI_BR_UCN_idx | PAPI_PRESET_MASK) /*Unconditional branch instructions executed */
 
#define PAPI_BR_CN   (PAPI_BR_CN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions executed */
 
#define PAPI_BR_TKN   (PAPI_BR_TKN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions taken */
 
#define PAPI_BR_NTK   (PAPI_BR_NTK_idx | PAPI_PRESET_MASK) /*Conditional branch instructions not taken */
 
#define PAPI_BR_MSP   (PAPI_BR_MSP_idx | PAPI_PRESET_MASK) /*Conditional branch instructions mispred */
 
#define PAPI_BR_PRC   (PAPI_BR_PRC_idx | PAPI_PRESET_MASK) /*Conditional branch instructions corr. pred */
 
#define PAPI_FMA_INS   (PAPI_FMA_INS_idx | PAPI_PRESET_MASK) /*FMA instructions completed */
 
#define PAPI_TOT_IIS   (PAPI_TOT_IIS_idx | PAPI_PRESET_MASK) /*Total instructions issued */
 
#define PAPI_TOT_INS   (PAPI_TOT_INS_idx | PAPI_PRESET_MASK) /*Total instructions executed */
 
#define PAPI_INT_INS   (PAPI_INT_INS_idx | PAPI_PRESET_MASK) /*Integer instructions executed */
 
#define PAPI_FP_INS   (PAPI_FP_INS_idx | PAPI_PRESET_MASK) /*Floating point instructions executed */
 
#define PAPI_LD_INS   (PAPI_LD_INS_idx | PAPI_PRESET_MASK) /*Load instructions executed */
 
#define PAPI_SR_INS   (PAPI_SR_INS_idx | PAPI_PRESET_MASK) /*Store instructions executed */
 
#define PAPI_BR_INS   (PAPI_BR_INS_idx | PAPI_PRESET_MASK) /*Total branch instructions executed */
 
#define PAPI_VEC_INS   (PAPI_VEC_INS_idx | PAPI_PRESET_MASK) /*Vector/SIMD instructions executed (could include integer) */
 
#define PAPI_RES_STL   (PAPI_RES_STL_idx | PAPI_PRESET_MASK) /*Cycles processor is stalled on resource */
 
#define PAPI_FP_STAL   (PAPI_FP_STAL_idx | PAPI_PRESET_MASK) /*Cycles any FP units are stalled */
 
#define PAPI_TOT_CYC   (PAPI_TOT_CYC_idx | PAPI_PRESET_MASK) /*Total cycles executed */
 
#define PAPI_LST_INS   (PAPI_LST_INS_idx | PAPI_PRESET_MASK) /*Total load/store inst. executed */
 
#define PAPI_SYC_INS   (PAPI_SYC_INS_idx | PAPI_PRESET_MASK) /*Sync. inst. executed */
 
#define PAPI_L1_DCH   (PAPI_L1_DCH_idx | PAPI_PRESET_MASK) /*L1 D Cache Hit */
 
#define PAPI_L2_DCH   (PAPI_L2_DCH_idx | PAPI_PRESET_MASK) /*L2 D Cache Hit */
 
#define PAPI_L1_DCA   (PAPI_L1_DCA_idx | PAPI_PRESET_MASK) /*L1 D Cache Access */
 
#define PAPI_L2_DCA   (PAPI_L2_DCA_idx | PAPI_PRESET_MASK) /*L2 D Cache Access */
 
#define PAPI_L3_DCA   (PAPI_L3_DCA_idx | PAPI_PRESET_MASK) /*L3 D Cache Access */
 
#define PAPI_L1_DCR   (PAPI_L1_DCR_idx | PAPI_PRESET_MASK) /*L1 D Cache Read */
 
#define PAPI_L2_DCR   (PAPI_L2_DCR_idx | PAPI_PRESET_MASK) /*L2 D Cache Read */
 
#define PAPI_L3_DCR   (PAPI_L3_DCR_idx | PAPI_PRESET_MASK) /*L3 D Cache Read */
 
#define PAPI_L1_DCW   (PAPI_L1_DCW_idx | PAPI_PRESET_MASK) /*L1 D Cache Write */
 
#define PAPI_L2_DCW   (PAPI_L2_DCW_idx | PAPI_PRESET_MASK) /*L2 D Cache Write */
 
#define PAPI_L3_DCW   (PAPI_L3_DCW_idx | PAPI_PRESET_MASK) /*L3 D Cache Write */
 
#define PAPI_L1_ICH   (PAPI_L1_ICH_idx | PAPI_PRESET_MASK) /*L1 instruction cache hits */
 
#define PAPI_L2_ICH   (PAPI_L2_ICH_idx | PAPI_PRESET_MASK) /*L2 instruction cache hits */
 
#define PAPI_L3_ICH   (PAPI_L3_ICH_idx | PAPI_PRESET_MASK) /*L3 instruction cache hits */
 
#define PAPI_L1_ICA   (PAPI_L1_ICA_idx | PAPI_PRESET_MASK) /*L1 instruction cache accesses */
 
#define PAPI_L2_ICA   (PAPI_L2_ICA_idx | PAPI_PRESET_MASK) /*L2 instruction cache accesses */
 
#define PAPI_L3_ICA   (PAPI_L3_ICA_idx | PAPI_PRESET_MASK) /*L3 instruction cache accesses */
 
#define PAPI_L1_ICR   (PAPI_L1_ICR_idx | PAPI_PRESET_MASK) /*L1 instruction cache reads */
 
#define PAPI_L2_ICR   (PAPI_L2_ICR_idx | PAPI_PRESET_MASK) /*L2 instruction cache reads */
 
#define PAPI_L3_ICR   (PAPI_L3_ICR_idx | PAPI_PRESET_MASK) /*L3 instruction cache reads */
 
#define PAPI_L1_ICW   (PAPI_L1_ICW_idx | PAPI_PRESET_MASK) /*L1 instruction cache writes */
 
#define PAPI_L2_ICW   (PAPI_L2_ICW_idx | PAPI_PRESET_MASK) /*L2 instruction cache writes */
 
#define PAPI_L3_ICW   (PAPI_L3_ICW_idx | PAPI_PRESET_MASK) /*L3 instruction cache writes */
 
#define PAPI_L1_TCH   (PAPI_L1_TCH_idx | PAPI_PRESET_MASK) /*L1 total cache hits */
 
#define PAPI_L2_TCH   (PAPI_L2_TCH_idx | PAPI_PRESET_MASK) /*L2 total cache hits */
 
#define PAPI_L3_TCH   (PAPI_L3_TCH_idx | PAPI_PRESET_MASK) /*L3 total cache hits */
 
#define PAPI_L1_TCA   (PAPI_L1_TCA_idx | PAPI_PRESET_MASK) /*L1 total cache accesses */
 
#define PAPI_L2_TCA   (PAPI_L2_TCA_idx | PAPI_PRESET_MASK) /*L2 total cache accesses */
 
#define PAPI_L3_TCA   (PAPI_L3_TCA_idx | PAPI_PRESET_MASK) /*L3 total cache accesses */
 
#define PAPI_L1_TCR   (PAPI_L1_TCR_idx | PAPI_PRESET_MASK) /*L1 total cache reads */
 
#define PAPI_L2_TCR   (PAPI_L2_TCR_idx | PAPI_PRESET_MASK) /*L2 total cache reads */
 
#define PAPI_L3_TCR   (PAPI_L3_TCR_idx | PAPI_PRESET_MASK) /*L3 total cache reads */
 
#define PAPI_L1_TCW   (PAPI_L1_TCW_idx | PAPI_PRESET_MASK) /*L1 total cache writes */
 
#define PAPI_L2_TCW   (PAPI_L2_TCW_idx | PAPI_PRESET_MASK) /*L2 total cache writes */
 
#define PAPI_L3_TCW   (PAPI_L3_TCW_idx | PAPI_PRESET_MASK) /*L3 total cache writes */
 
#define PAPI_FML_INS   (PAPI_FML_INS_idx | PAPI_PRESET_MASK) /*FM ins */
 
#define PAPI_FAD_INS   (PAPI_FAD_INS_idx | PAPI_PRESET_MASK) /*FA ins */
 
#define PAPI_FDV_INS   (PAPI_FDV_INS_idx | PAPI_PRESET_MASK) /*FD ins */
 
#define PAPI_FSQ_INS   (PAPI_FSQ_INS_idx | PAPI_PRESET_MASK) /*FSq ins */
 
#define PAPI_FNV_INS   (PAPI_FNV_INS_idx | PAPI_PRESET_MASK) /*Finv ins */
 
#define PAPI_FP_OPS   (PAPI_FP_OPS_idx | PAPI_PRESET_MASK) /*Floating point operations executed */
 
#define PAPI_SP_OPS   (PAPI_SP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled single precision vector operations */
 
#define PAPI_DP_OPS   (PAPI_DP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled double precision vector operations */
 
#define PAPI_VEC_SP   (PAPI_VEC_SP_idx | PAPI_PRESET_MASK) /* Single precision vector/SIMD instructions */
 
#define PAPI_VEC_DP   (PAPI_VEC_DP_idx | PAPI_PRESET_MASK) /* Double precision vector/SIMD instructions */
 
#define PAPI_REF_CYC   (PAPI_REF_CYC_idx | PAPI_PRESET_MASK) /* Reference clock cycles */
 
#define PAPI_END   (PAPI_END_idx | PAPI_PRESET_MASK) /*This should always be last! */
 

Enumerations

enum  {
  PAPI_L1_DCM_idx = 0, PAPI_L1_ICM_idx, PAPI_L2_DCM_idx, PAPI_L2_ICM_idx,
  PAPI_L3_DCM_idx, PAPI_L3_ICM_idx, PAPI_L1_TCM_idx, PAPI_L2_TCM_idx,
  PAPI_L3_TCM_idx, PAPI_CA_SNP_idx, PAPI_CA_SHR_idx, PAPI_CA_CLN_idx,
  PAPI_CA_INV_idx, PAPI_CA_ITV_idx, PAPI_L3_LDM_idx, PAPI_L3_STM_idx,
  PAPI_BRU_IDL_idx, PAPI_FXU_IDL_idx, PAPI_FPU_IDL_idx, PAPI_LSU_IDL_idx,
  PAPI_TLB_DM_idx, PAPI_TLB_IM_idx, PAPI_TLB_TL_idx, PAPI_L1_LDM_idx,
  PAPI_L1_STM_idx, PAPI_L2_LDM_idx, PAPI_L2_STM_idx, PAPI_BTAC_M_idx,
  PAPI_PRF_DM_idx, PAPI_L3_DCH_idx, PAPI_TLB_SD_idx, PAPI_CSR_FAL_idx,
  PAPI_CSR_SUC_idx, PAPI_CSR_TOT_idx, PAPI_MEM_SCY_idx, PAPI_MEM_RCY_idx,
  PAPI_MEM_WCY_idx, PAPI_STL_ICY_idx, PAPI_FUL_ICY_idx, PAPI_STL_CCY_idx,
  PAPI_FUL_CCY_idx, PAPI_HW_INT_idx, PAPI_BR_UCN_idx, PAPI_BR_CN_idx,
  PAPI_BR_TKN_idx, PAPI_BR_NTK_idx, PAPI_BR_MSP_idx, PAPI_BR_PRC_idx,
  PAPI_FMA_INS_idx, PAPI_TOT_IIS_idx, PAPI_TOT_INS_idx, PAPI_INT_INS_idx,
  PAPI_FP_INS_idx, PAPI_LD_INS_idx, PAPI_SR_INS_idx, PAPI_BR_INS_idx,
  PAPI_VEC_INS_idx, PAPI_RES_STL_idx, PAPI_FP_STAL_idx, PAPI_TOT_CYC_idx,
  PAPI_LST_INS_idx, PAPI_SYC_INS_idx, PAPI_L1_DCH_idx, PAPI_L2_DCH_idx,
  PAPI_L1_DCA_idx, PAPI_L2_DCA_idx, PAPI_L3_DCA_idx, PAPI_L1_DCR_idx,
  PAPI_L2_DCR_idx, PAPI_L3_DCR_idx, PAPI_L1_DCW_idx, PAPI_L2_DCW_idx,
  PAPI_L3_DCW_idx, PAPI_L1_ICH_idx, PAPI_L2_ICH_idx, PAPI_L3_ICH_idx,
  PAPI_L1_ICA_idx, PAPI_L2_ICA_idx, PAPI_L3_ICA_idx, PAPI_L1_ICR_idx,
  PAPI_L2_ICR_idx, PAPI_L3_ICR_idx, PAPI_L1_ICW_idx, PAPI_L2_ICW_idx,
  PAPI_L3_ICW_idx, PAPI_L1_TCH_idx, PAPI_L2_TCH_idx, PAPI_L3_TCH_idx,
  PAPI_L1_TCA_idx, PAPI_L2_TCA_idx, PAPI_L3_TCA_idx, PAPI_L1_TCR_idx,
  PAPI_L2_TCR_idx, PAPI_L3_TCR_idx, PAPI_L1_TCW_idx, PAPI_L2_TCW_idx,
  PAPI_L3_TCW_idx, PAPI_FML_INS_idx, PAPI_FAD_INS_idx, PAPI_FDV_INS_idx,
  PAPI_FSQ_INS_idx, PAPI_FNV_INS_idx, PAPI_FP_OPS_idx, PAPI_SP_OPS_idx,
  PAPI_DP_OPS_idx, PAPI_VEC_SP_idx, PAPI_VEC_DP_idx, PAPI_REF_CYC_idx,
  PAPI_END_idx
}
 

Macro Definition Documentation

#define PAPI_BR_CN   (PAPI_BR_CN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions executed */

Definition at line 209 of file papiStdEventDefs.h.

#define PAPI_BR_INS   (PAPI_BR_INS_idx | PAPI_PRESET_MASK) /*Total branch instructions executed */

Definition at line 221 of file papiStdEventDefs.h.

#define PAPI_BR_MSP   (PAPI_BR_MSP_idx | PAPI_PRESET_MASK) /*Conditional branch instructions mispred */

Definition at line 212 of file papiStdEventDefs.h.

#define PAPI_BR_NTK   (PAPI_BR_NTK_idx | PAPI_PRESET_MASK) /*Conditional branch instructions not taken */

Definition at line 211 of file papiStdEventDefs.h.

#define PAPI_BR_PRC   (PAPI_BR_PRC_idx | PAPI_PRESET_MASK) /*Conditional branch instructions corr. pred */

Definition at line 213 of file papiStdEventDefs.h.

#define PAPI_BR_TKN   (PAPI_BR_TKN_idx | PAPI_PRESET_MASK) /*Conditional branch instructions taken */

Definition at line 210 of file papiStdEventDefs.h.

#define PAPI_BR_UCN   (PAPI_BR_UCN_idx | PAPI_PRESET_MASK) /*Unconditional branch instructions executed */

Definition at line 208 of file papiStdEventDefs.h.

#define PAPI_BRU_IDL   (PAPI_BRU_IDL_idx | PAPI_PRESET_MASK) /*Cycles branch units are idle */

Definition at line 182 of file papiStdEventDefs.h.

#define PAPI_BTAC_M   (PAPI_BTAC_M_idx | PAPI_PRESET_MASK) /*BTAC miss */

Definition at line 193 of file papiStdEventDefs.h.

#define PAPI_CA_CLN   (PAPI_CA_CLN_idx | PAPI_PRESET_MASK) /*Request for clean cache line (SMP) */

Definition at line 177 of file papiStdEventDefs.h.

#define PAPI_CA_INV   (PAPI_CA_INV_idx | PAPI_PRESET_MASK) /*Request for cache line Invalidation (SMP) */

Definition at line 178 of file papiStdEventDefs.h.

#define PAPI_CA_ITV   (PAPI_CA_ITV_idx | PAPI_PRESET_MASK) /*Request for cache line Intervention (SMP) */

Definition at line 179 of file papiStdEventDefs.h.

#define PAPI_CA_SHR   (PAPI_CA_SHR_idx | PAPI_PRESET_MASK) /*Request for shared cache line (SMP) */

Definition at line 176 of file papiStdEventDefs.h.

#define PAPI_CA_SNP   (PAPI_CA_SNP_idx | PAPI_PRESET_MASK) /*Snoops */

Definition at line 175 of file papiStdEventDefs.h.

#define PAPI_CSR_FAL   (PAPI_CSR_FAL_idx | PAPI_PRESET_MASK) /*Failed store conditional instructions */

Definition at line 197 of file papiStdEventDefs.h.

#define PAPI_CSR_SUC   (PAPI_CSR_SUC_idx | PAPI_PRESET_MASK) /*Successful store conditional instructions */

Definition at line 198 of file papiStdEventDefs.h.

#define PAPI_CSR_TOT   (PAPI_CSR_TOT_idx | PAPI_PRESET_MASK) /*Total store conditional instructions */

Definition at line 199 of file papiStdEventDefs.h.

#define PAPI_DP_OPS   (PAPI_DP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled double precision vector operations */

Definition at line 270 of file papiStdEventDefs.h.

#define PAPI_END   (PAPI_END_idx | PAPI_PRESET_MASK) /*This should always be last! */

Definition at line 275 of file papiStdEventDefs.h.

#define PAPI_FAD_INS   (PAPI_FAD_INS_idx | PAPI_PRESET_MASK) /*FA ins */

Definition at line 264 of file papiStdEventDefs.h.

#define PAPI_FDV_INS   (PAPI_FDV_INS_idx | PAPI_PRESET_MASK) /*FD ins */

Definition at line 265 of file papiStdEventDefs.h.

#define PAPI_FMA_INS   (PAPI_FMA_INS_idx | PAPI_PRESET_MASK) /*FMA instructions completed */

Definition at line 214 of file papiStdEventDefs.h.

#define PAPI_FML_INS   (PAPI_FML_INS_idx | PAPI_PRESET_MASK) /*FM ins */

Definition at line 263 of file papiStdEventDefs.h.

#define PAPI_FNV_INS   (PAPI_FNV_INS_idx | PAPI_PRESET_MASK) /*Finv ins */

Definition at line 267 of file papiStdEventDefs.h.

#define PAPI_FP_INS   (PAPI_FP_INS_idx | PAPI_PRESET_MASK) /*Floating point instructions executed */

Definition at line 218 of file papiStdEventDefs.h.

#define PAPI_FP_OPS   (PAPI_FP_OPS_idx | PAPI_PRESET_MASK) /*Floating point operations executed */

Definition at line 268 of file papiStdEventDefs.h.

#define PAPI_FP_STAL   (PAPI_FP_STAL_idx | PAPI_PRESET_MASK) /*Cycles any FP units are stalled */

Definition at line 224 of file papiStdEventDefs.h.

#define PAPI_FPU_IDL   (PAPI_FPU_IDL_idx | PAPI_PRESET_MASK) /*Cycles floating point units are idle */

Definition at line 184 of file papiStdEventDefs.h.

#define PAPI_FSQ_INS   (PAPI_FSQ_INS_idx | PAPI_PRESET_MASK) /*FSq ins */

Definition at line 266 of file papiStdEventDefs.h.

#define PAPI_FUL_CCY   (PAPI_FUL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Completion */

Definition at line 206 of file papiStdEventDefs.h.

#define PAPI_FUL_ICY   (PAPI_FUL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with Maximum Instruction Issue */

Definition at line 204 of file papiStdEventDefs.h.

#define PAPI_FXU_IDL   (PAPI_FXU_IDL_idx | PAPI_PRESET_MASK) /*Cycles integer units are idle */

Definition at line 183 of file papiStdEventDefs.h.

#define PAPI_HW_INT   (PAPI_HW_INT_idx | PAPI_PRESET_MASK) /*Hardware interrupts */

Definition at line 207 of file papiStdEventDefs.h.

#define PAPI_INT_INS   (PAPI_INT_INS_idx | PAPI_PRESET_MASK) /*Integer instructions executed */

Definition at line 217 of file papiStdEventDefs.h.

#define PAPI_L1_DCA   (PAPI_L1_DCA_idx | PAPI_PRESET_MASK) /*L1 D Cache Access */

Definition at line 230 of file papiStdEventDefs.h.

#define PAPI_L1_DCH   (PAPI_L1_DCH_idx | PAPI_PRESET_MASK) /*L1 D Cache Hit */

Definition at line 228 of file papiStdEventDefs.h.

#define PAPI_L1_DCM   (PAPI_L1_DCM_idx | PAPI_PRESET_MASK) /*Level 1 data cache misses */

Definition at line 166 of file papiStdEventDefs.h.

#define PAPI_L1_DCR   (PAPI_L1_DCR_idx | PAPI_PRESET_MASK) /*L1 D Cache Read */

Definition at line 233 of file papiStdEventDefs.h.

#define PAPI_L1_DCW   (PAPI_L1_DCW_idx | PAPI_PRESET_MASK) /*L1 D Cache Write */

Definition at line 236 of file papiStdEventDefs.h.

#define PAPI_L1_ICA   (PAPI_L1_ICA_idx | PAPI_PRESET_MASK) /*L1 instruction cache accesses */

Definition at line 242 of file papiStdEventDefs.h.

#define PAPI_L1_ICH   (PAPI_L1_ICH_idx | PAPI_PRESET_MASK) /*L1 instruction cache hits */

Definition at line 239 of file papiStdEventDefs.h.

#define PAPI_L1_ICM   (PAPI_L1_ICM_idx | PAPI_PRESET_MASK) /*Level 1 instruction cache misses */

Definition at line 167 of file papiStdEventDefs.h.

#define PAPI_L1_ICR   (PAPI_L1_ICR_idx | PAPI_PRESET_MASK) /*L1 instruction cache reads */

Definition at line 245 of file papiStdEventDefs.h.

#define PAPI_L1_ICW   (PAPI_L1_ICW_idx | PAPI_PRESET_MASK) /*L1 instruction cache writes */

Definition at line 248 of file papiStdEventDefs.h.

#define PAPI_L1_LDM   (PAPI_L1_LDM_idx | PAPI_PRESET_MASK) /*Level 1 load misses */

Definition at line 189 of file papiStdEventDefs.h.

#define PAPI_L1_STM   (PAPI_L1_STM_idx | PAPI_PRESET_MASK) /*Level 1 store misses */

Definition at line 190 of file papiStdEventDefs.h.

#define PAPI_L1_TCA   (PAPI_L1_TCA_idx | PAPI_PRESET_MASK) /*L1 total cache accesses */

Definition at line 254 of file papiStdEventDefs.h.

#define PAPI_L1_TCH   (PAPI_L1_TCH_idx | PAPI_PRESET_MASK) /*L1 total cache hits */

Definition at line 251 of file papiStdEventDefs.h.

#define PAPI_L1_TCM   (PAPI_L1_TCM_idx | PAPI_PRESET_MASK) /*Level 1 total cache misses */

Definition at line 172 of file papiStdEventDefs.h.

#define PAPI_L1_TCR   (PAPI_L1_TCR_idx | PAPI_PRESET_MASK) /*L1 total cache reads */

Definition at line 257 of file papiStdEventDefs.h.

#define PAPI_L1_TCW   (PAPI_L1_TCW_idx | PAPI_PRESET_MASK) /*L1 total cache writes */

Definition at line 260 of file papiStdEventDefs.h.

#define PAPI_L2_DCA   (PAPI_L2_DCA_idx | PAPI_PRESET_MASK) /*L2 D Cache Access */

Definition at line 231 of file papiStdEventDefs.h.

#define PAPI_L2_DCH   (PAPI_L2_DCH_idx | PAPI_PRESET_MASK) /*L2 D Cache Hit */

Definition at line 229 of file papiStdEventDefs.h.

#define PAPI_L2_DCM   (PAPI_L2_DCM_idx | PAPI_PRESET_MASK) /*Level 2 data cache misses */

Definition at line 168 of file papiStdEventDefs.h.

#define PAPI_L2_DCR   (PAPI_L2_DCR_idx | PAPI_PRESET_MASK) /*L2 D Cache Read */

Definition at line 234 of file papiStdEventDefs.h.

#define PAPI_L2_DCW   (PAPI_L2_DCW_idx | PAPI_PRESET_MASK) /*L2 D Cache Write */

Definition at line 237 of file papiStdEventDefs.h.

#define PAPI_L2_ICA   (PAPI_L2_ICA_idx | PAPI_PRESET_MASK) /*L2 instruction cache accesses */

Definition at line 243 of file papiStdEventDefs.h.

#define PAPI_L2_ICH   (PAPI_L2_ICH_idx | PAPI_PRESET_MASK) /*L2 instruction cache hits */

Definition at line 240 of file papiStdEventDefs.h.

#define PAPI_L2_ICM   (PAPI_L2_ICM_idx | PAPI_PRESET_MASK) /*Level 2 instruction cache misses */

Definition at line 169 of file papiStdEventDefs.h.

#define PAPI_L2_ICR   (PAPI_L2_ICR_idx | PAPI_PRESET_MASK) /*L2 instruction cache reads */

Definition at line 246 of file papiStdEventDefs.h.

#define PAPI_L2_ICW   (PAPI_L2_ICW_idx | PAPI_PRESET_MASK) /*L2 instruction cache writes */

Definition at line 249 of file papiStdEventDefs.h.

#define PAPI_L2_LDM   (PAPI_L2_LDM_idx | PAPI_PRESET_MASK) /*Level 2 load misses */

Definition at line 191 of file papiStdEventDefs.h.

#define PAPI_L2_STM   (PAPI_L2_STM_idx | PAPI_PRESET_MASK) /*Level 2 store misses */

Definition at line 192 of file papiStdEventDefs.h.

#define PAPI_L2_TCA   (PAPI_L2_TCA_idx | PAPI_PRESET_MASK) /*L2 total cache accesses */

Definition at line 255 of file papiStdEventDefs.h.

#define PAPI_L2_TCH   (PAPI_L2_TCH_idx | PAPI_PRESET_MASK) /*L2 total cache hits */

Definition at line 252 of file papiStdEventDefs.h.

#define PAPI_L2_TCM   (PAPI_L2_TCM_idx | PAPI_PRESET_MASK) /*Level 2 total cache misses */

Definition at line 173 of file papiStdEventDefs.h.

#define PAPI_L2_TCR   (PAPI_L2_TCR_idx | PAPI_PRESET_MASK) /*L2 total cache reads */

Definition at line 258 of file papiStdEventDefs.h.

#define PAPI_L2_TCW   (PAPI_L2_TCW_idx | PAPI_PRESET_MASK) /*L2 total cache writes */

Definition at line 261 of file papiStdEventDefs.h.

#define PAPI_L3_DCA   (PAPI_L3_DCA_idx | PAPI_PRESET_MASK) /*L3 D Cache Access */

Definition at line 232 of file papiStdEventDefs.h.

#define PAPI_L3_DCH   (PAPI_L3_DCH_idx | PAPI_PRESET_MASK) /*Level 3 Data Cache Hit */

Definition at line 195 of file papiStdEventDefs.h.

#define PAPI_L3_DCM   (PAPI_L3_DCM_idx | PAPI_PRESET_MASK) /*Level 3 data cache misses */

Definition at line 170 of file papiStdEventDefs.h.

#define PAPI_L3_DCR   (PAPI_L3_DCR_idx | PAPI_PRESET_MASK) /*L3 D Cache Read */

Definition at line 235 of file papiStdEventDefs.h.

#define PAPI_L3_DCW   (PAPI_L3_DCW_idx | PAPI_PRESET_MASK) /*L3 D Cache Write */

Definition at line 238 of file papiStdEventDefs.h.

#define PAPI_L3_ICA   (PAPI_L3_ICA_idx | PAPI_PRESET_MASK) /*L3 instruction cache accesses */

Definition at line 244 of file papiStdEventDefs.h.

#define PAPI_L3_ICH   (PAPI_L3_ICH_idx | PAPI_PRESET_MASK) /*L3 instruction cache hits */

Definition at line 241 of file papiStdEventDefs.h.

#define PAPI_L3_ICM   (PAPI_L3_ICM_idx | PAPI_PRESET_MASK) /*Level 3 instruction cache misses */

Definition at line 171 of file papiStdEventDefs.h.

#define PAPI_L3_ICR   (PAPI_L3_ICR_idx | PAPI_PRESET_MASK) /*L3 instruction cache reads */

Definition at line 247 of file papiStdEventDefs.h.

#define PAPI_L3_ICW   (PAPI_L3_ICW_idx | PAPI_PRESET_MASK) /*L3 instruction cache writes */

Definition at line 250 of file papiStdEventDefs.h.

#define PAPI_L3_LDM   (PAPI_L3_LDM_idx | PAPI_PRESET_MASK) /*Level 3 load misses */

Definition at line 180 of file papiStdEventDefs.h.

#define PAPI_L3_STM   (PAPI_L3_STM_idx | PAPI_PRESET_MASK) /*Level 3 store misses */

Definition at line 181 of file papiStdEventDefs.h.

#define PAPI_L3_TCA   (PAPI_L3_TCA_idx | PAPI_PRESET_MASK) /*L3 total cache accesses */

Definition at line 256 of file papiStdEventDefs.h.

#define PAPI_L3_TCH   (PAPI_L3_TCH_idx | PAPI_PRESET_MASK) /*L3 total cache hits */

Definition at line 253 of file papiStdEventDefs.h.

#define PAPI_L3_TCM   (PAPI_L3_TCM_idx | PAPI_PRESET_MASK) /*Level 3 total cache misses */

Definition at line 174 of file papiStdEventDefs.h.

#define PAPI_L3_TCR   (PAPI_L3_TCR_idx | PAPI_PRESET_MASK) /*L3 total cache reads */

Definition at line 259 of file papiStdEventDefs.h.

#define PAPI_L3_TCW   (PAPI_L3_TCW_idx | PAPI_PRESET_MASK) /*L3 total cache writes */

Definition at line 262 of file papiStdEventDefs.h.

#define PAPI_LD_INS   (PAPI_LD_INS_idx | PAPI_PRESET_MASK) /*Load instructions executed */

Definition at line 219 of file papiStdEventDefs.h.

#define PAPI_LST_INS   (PAPI_LST_INS_idx | PAPI_PRESET_MASK) /*Total load/store inst. executed */

Definition at line 226 of file papiStdEventDefs.h.

#define PAPI_LSU_IDL   (PAPI_LSU_IDL_idx | PAPI_PRESET_MASK) /*Cycles load/store units are idle */

Definition at line 185 of file papiStdEventDefs.h.

#define PAPI_MAX_PRESET_EVENTS   128 /*The maxmimum number of preset events */

Definition at line 34 of file papiStdEventDefs.h.

#define PAPI_MEM_RCY   (PAPI_MEM_RCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Read */

Definition at line 201 of file papiStdEventDefs.h.

#define PAPI_MEM_SCY   (PAPI_MEM_SCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Access */

Definition at line 200 of file papiStdEventDefs.h.

#define PAPI_MEM_WCY   (PAPI_MEM_WCY_idx | PAPI_PRESET_MASK) /*Cycles Stalled Waiting for Memory Write */

Definition at line 202 of file papiStdEventDefs.h.

#define PAPI_NATIVE_AND_MASK   0xBFFFFFFF /* this masks just the native bit */

Definition at line 32 of file papiStdEventDefs.h.

#define PAPI_NATIVE_MASK   0x40000000

Definition at line 30 of file papiStdEventDefs.h.

#define PAPI_PRESET_AND_MASK   0x7FFFFFFF

Definition at line 31 of file papiStdEventDefs.h.

#define PAPI_PRESET_MASK   ((int)0x80000000)

Definition at line 29 of file papiStdEventDefs.h.

#define PAPI_PRF_DM   (PAPI_PRF_DM_idx | PAPI_PRESET_MASK) /*Prefetch data instruction caused a miss */

Definition at line 194 of file papiStdEventDefs.h.

#define PAPI_REF_CYC   (PAPI_REF_CYC_idx | PAPI_PRESET_MASK) /* Reference clock cycles */

Definition at line 273 of file papiStdEventDefs.h.

#define PAPI_RES_STL   (PAPI_RES_STL_idx | PAPI_PRESET_MASK) /*Cycles processor is stalled on resource */

Definition at line 223 of file papiStdEventDefs.h.

#define PAPI_SP_OPS   (PAPI_SP_OPS_idx | PAPI_PRESET_MASK) /* Floating point operations executed; optimized to count scaled single precision vector operations */

Definition at line 269 of file papiStdEventDefs.h.

#define PAPI_SR_INS   (PAPI_SR_INS_idx | PAPI_PRESET_MASK) /*Store instructions executed */

Definition at line 220 of file papiStdEventDefs.h.

#define PAPI_STL_CCY   (PAPI_STL_CCY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Completion */

Definition at line 205 of file papiStdEventDefs.h.

#define PAPI_STL_ICY   (PAPI_STL_ICY_idx | PAPI_PRESET_MASK) /*Cycles with No Instruction Issue */

Definition at line 203 of file papiStdEventDefs.h.

#define PAPI_SYC_INS   (PAPI_SYC_INS_idx | PAPI_PRESET_MASK) /*Sync. inst. executed */

Definition at line 227 of file papiStdEventDefs.h.

#define PAPI_TLB_DM   (PAPI_TLB_DM_idx | PAPI_PRESET_MASK) /*Data translation lookaside buffer misses */

Definition at line 186 of file papiStdEventDefs.h.

#define PAPI_TLB_IM   (PAPI_TLB_IM_idx | PAPI_PRESET_MASK) /*Instr translation lookaside buffer misses */

Definition at line 187 of file papiStdEventDefs.h.

#define PAPI_TLB_SD   (PAPI_TLB_SD_idx | PAPI_PRESET_MASK) /*Xlation lookaside buffer shootdowns (SMP) */

Definition at line 196 of file papiStdEventDefs.h.

#define PAPI_TLB_TL   (PAPI_TLB_TL_idx | PAPI_PRESET_MASK) /*Total translation lookaside buffer misses */

Definition at line 188 of file papiStdEventDefs.h.

#define PAPI_TOT_CYC   (PAPI_TOT_CYC_idx | PAPI_PRESET_MASK) /*Total cycles executed */

Definition at line 225 of file papiStdEventDefs.h.

#define PAPI_TOT_IIS   (PAPI_TOT_IIS_idx | PAPI_PRESET_MASK) /*Total instructions issued */

Definition at line 215 of file papiStdEventDefs.h.

#define PAPI_TOT_INS   (PAPI_TOT_INS_idx | PAPI_PRESET_MASK) /*Total instructions executed */

Definition at line 216 of file papiStdEventDefs.h.

#define PAPI_VEC_DP   (PAPI_VEC_DP_idx | PAPI_PRESET_MASK) /* Double precision vector/SIMD instructions */

Definition at line 272 of file papiStdEventDefs.h.

#define PAPI_VEC_INS   (PAPI_VEC_INS_idx | PAPI_PRESET_MASK) /*Vector/SIMD instructions executed (could include integer) */

Definition at line 222 of file papiStdEventDefs.h.

#define PAPI_VEC_SP   (PAPI_VEC_SP_idx | PAPI_PRESET_MASK) /* Single precision vector/SIMD instructions */

Definition at line 271 of file papiStdEventDefs.h.

Enumeration Type Documentation

anonymous enum
Enumerator
PAPI_L1_DCM_idx 
PAPI_L1_ICM_idx 
PAPI_L2_DCM_idx 
PAPI_L2_ICM_idx 
PAPI_L3_DCM_idx 
PAPI_L3_ICM_idx 
PAPI_L1_TCM_idx 
PAPI_L2_TCM_idx 
PAPI_L3_TCM_idx 
PAPI_CA_SNP_idx 
PAPI_CA_SHR_idx 
PAPI_CA_CLN_idx 
PAPI_CA_INV_idx 
PAPI_CA_ITV_idx 
PAPI_L3_LDM_idx 
PAPI_L3_STM_idx 
PAPI_BRU_IDL_idx 
PAPI_FXU_IDL_idx 
PAPI_FPU_IDL_idx 
PAPI_LSU_IDL_idx 
PAPI_TLB_DM_idx 
PAPI_TLB_IM_idx 
PAPI_TLB_TL_idx 
PAPI_L1_LDM_idx 
PAPI_L1_STM_idx 
PAPI_L2_LDM_idx 
PAPI_L2_STM_idx 
PAPI_BTAC_M_idx 
PAPI_PRF_DM_idx 
PAPI_L3_DCH_idx 
PAPI_TLB_SD_idx 
PAPI_CSR_FAL_idx 
PAPI_CSR_SUC_idx 
PAPI_CSR_TOT_idx 
PAPI_MEM_SCY_idx 
PAPI_MEM_RCY_idx 
PAPI_MEM_WCY_idx 
PAPI_STL_ICY_idx 
PAPI_FUL_ICY_idx 
PAPI_STL_CCY_idx 
PAPI_FUL_CCY_idx 
PAPI_HW_INT_idx 
PAPI_BR_UCN_idx 
PAPI_BR_CN_idx 
PAPI_BR_TKN_idx 
PAPI_BR_NTK_idx 
PAPI_BR_MSP_idx 
PAPI_BR_PRC_idx 
PAPI_FMA_INS_idx 
PAPI_TOT_IIS_idx 
PAPI_TOT_INS_idx 
PAPI_INT_INS_idx 
PAPI_FP_INS_idx 
PAPI_LD_INS_idx 
PAPI_SR_INS_idx 
PAPI_BR_INS_idx 
PAPI_VEC_INS_idx 
PAPI_RES_STL_idx 
PAPI_FP_STAL_idx 
PAPI_TOT_CYC_idx 
PAPI_LST_INS_idx 
PAPI_SYC_INS_idx 
PAPI_L1_DCH_idx 
PAPI_L2_DCH_idx 
PAPI_L1_DCA_idx 
PAPI_L2_DCA_idx 
PAPI_L3_DCA_idx 
PAPI_L1_DCR_idx 
PAPI_L2_DCR_idx 
PAPI_L3_DCR_idx 
PAPI_L1_DCW_idx 
PAPI_L2_DCW_idx 
PAPI_L3_DCW_idx 
PAPI_L1_ICH_idx 
PAPI_L2_ICH_idx 
PAPI_L3_ICH_idx 
PAPI_L1_ICA_idx 
PAPI_L2_ICA_idx 
PAPI_L3_ICA_idx 
PAPI_L1_ICR_idx 
PAPI_L2_ICR_idx 
PAPI_L3_ICR_idx 
PAPI_L1_ICW_idx 
PAPI_L2_ICW_idx 
PAPI_L3_ICW_idx 
PAPI_L1_TCH_idx 
PAPI_L2_TCH_idx 
PAPI_L3_TCH_idx 
PAPI_L1_TCA_idx 
PAPI_L2_TCA_idx 
PAPI_L3_TCA_idx 
PAPI_L1_TCR_idx 
PAPI_L2_TCR_idx 
PAPI_L3_TCR_idx 
PAPI_L1_TCW_idx 
PAPI_L2_TCW_idx 
PAPI_L3_TCW_idx 
PAPI_FML_INS_idx 
PAPI_FAD_INS_idx 
PAPI_FDV_INS_idx 
PAPI_FSQ_INS_idx 
PAPI_FNV_INS_idx 
PAPI_FP_OPS_idx 
PAPI_SP_OPS_idx 
PAPI_DP_OPS_idx 
PAPI_VEC_SP_idx 
PAPI_VEC_DP_idx 
PAPI_REF_CYC_idx 
PAPI_END_idx 

Definition at line 47 of file papiStdEventDefs.h.

48 {
49  PAPI_L1_DCM_idx = 0, /*Level 1 data cache misses */
50  PAPI_L1_ICM_idx, /*Level 1 instruction cache misses */
51  PAPI_L2_DCM_idx, /*Level 2 data cache misses */
52  PAPI_L2_ICM_idx, /*Level 2 instruction cache misses */
53  PAPI_L3_DCM_idx, /*Level 3 data cache misses */
54  PAPI_L3_ICM_idx, /*Level 3 instruction cache misses */
55  PAPI_L1_TCM_idx, /*Level 1 total cache misses */
56  PAPI_L2_TCM_idx, /*Level 2 total cache misses */
57  PAPI_L3_TCM_idx, /*Level 3 total cache misses */
58  PAPI_CA_SNP_idx, /*Snoops */
59  PAPI_CA_SHR_idx, /*Request for shared cache line (SMP) */
60  PAPI_CA_CLN_idx, /*Request for clean cache line (SMP) */
61  PAPI_CA_INV_idx, /*Request for cache line Invalidation (SMP) */
62  PAPI_CA_ITV_idx, /*Request for cache line Intervention (SMP) */
63  PAPI_L3_LDM_idx, /*Level 3 load misses */
64  PAPI_L3_STM_idx, /*Level 3 store misses */
65 /* 0x10 */
66  PAPI_BRU_IDL_idx, /*Cycles branch units are idle */
67  PAPI_FXU_IDL_idx, /*Cycles integer units are idle */
68  PAPI_FPU_IDL_idx, /*Cycles floating point units are idle */
69  PAPI_LSU_IDL_idx, /*Cycles load/store units are idle */
70  PAPI_TLB_DM_idx, /*Data translation lookaside buffer misses */
71  PAPI_TLB_IM_idx, /*Instr translation lookaside buffer misses */
72  PAPI_TLB_TL_idx, /*Total translation lookaside buffer misses */
73  PAPI_L1_LDM_idx, /*Level 1 load misses */
74  PAPI_L1_STM_idx, /*Level 1 store misses */
75  PAPI_L2_LDM_idx, /*Level 2 load misses */
76  PAPI_L2_STM_idx, /*Level 2 store misses */
77  PAPI_BTAC_M_idx, /*BTAC miss */
78  PAPI_PRF_DM_idx, /*Prefetch data instruction caused a miss */
79  PAPI_L3_DCH_idx, /*Level 3 Data Cache Hit */
80  PAPI_TLB_SD_idx, /*Xlation lookaside buffer shootdowns (SMP) */
81  PAPI_CSR_FAL_idx, /*Failed store conditional instructions */
82 /* 0x20 */
83  PAPI_CSR_SUC_idx, /*Successful store conditional instructions */
84  PAPI_CSR_TOT_idx, /*Total store conditional instructions */
85  PAPI_MEM_SCY_idx, /*Cycles Stalled Waiting for Memory Access */
86  PAPI_MEM_RCY_idx, /*Cycles Stalled Waiting for Memory Read */
87  PAPI_MEM_WCY_idx, /*Cycles Stalled Waiting for Memory Write */
88  PAPI_STL_ICY_idx, /*Cycles with No Instruction Issue */
89  PAPI_FUL_ICY_idx, /*Cycles with Maximum Instruction Issue */
90  PAPI_STL_CCY_idx, /*Cycles with No Instruction Completion */
91  PAPI_FUL_CCY_idx, /*Cycles with Maximum Instruction Completion */
92  PAPI_HW_INT_idx, /*Hardware interrupts */
93  PAPI_BR_UCN_idx, /*Unconditional branch instructions executed */
94  PAPI_BR_CN_idx, /*Conditional branch instructions executed */
95  PAPI_BR_TKN_idx, /*Conditional branch instructions taken */
96  PAPI_BR_NTK_idx, /*Conditional branch instructions not taken */
97  PAPI_BR_MSP_idx, /*Conditional branch instructions mispred */
98  PAPI_BR_PRC_idx, /*Conditional branch instructions corr. pred */
99 /* 0x30 */
100  PAPI_FMA_INS_idx, /*FMA instructions completed */
101  PAPI_TOT_IIS_idx, /*Total instructions issued */
102  PAPI_TOT_INS_idx, /*Total instructions executed */
103  PAPI_INT_INS_idx, /*Integer instructions executed */
104  PAPI_FP_INS_idx, /*Floating point instructions executed */
105  PAPI_LD_INS_idx, /*Load instructions executed */
106  PAPI_SR_INS_idx, /*Store instructions executed */
107  PAPI_BR_INS_idx, /*Total branch instructions executed */
108  PAPI_VEC_INS_idx, /*Vector/SIMD instructions executed (could include integer) */
109  PAPI_RES_STL_idx, /*Cycles processor is stalled on resource */
110  PAPI_FP_STAL_idx, /*Cycles any FP units are stalled */
111  PAPI_TOT_CYC_idx, /*Total cycles executed */
112  PAPI_LST_INS_idx, /*Total load/store inst. executed */
113  PAPI_SYC_INS_idx, /*Sync. inst. executed */
114  PAPI_L1_DCH_idx, /*L1 D Cache Hit */
115  PAPI_L2_DCH_idx, /*L2 D Cache Hit */
116  /* 0x40 */
117  PAPI_L1_DCA_idx, /*L1 D Cache Access */
118  PAPI_L2_DCA_idx, /*L2 D Cache Access */
119  PAPI_L3_DCA_idx, /*L3 D Cache Access */
120  PAPI_L1_DCR_idx, /*L1 D Cache Read */
121  PAPI_L2_DCR_idx, /*L2 D Cache Read */
122  PAPI_L3_DCR_idx, /*L3 D Cache Read */
123  PAPI_L1_DCW_idx, /*L1 D Cache Write */
124  PAPI_L2_DCW_idx, /*L2 D Cache Write */
125  PAPI_L3_DCW_idx, /*L3 D Cache Write */
126  PAPI_L1_ICH_idx, /*L1 instruction cache hits */
127  PAPI_L2_ICH_idx, /*L2 instruction cache hits */
128  PAPI_L3_ICH_idx, /*L3 instruction cache hits */
129  PAPI_L1_ICA_idx, /*L1 instruction cache accesses */
130  PAPI_L2_ICA_idx, /*L2 instruction cache accesses */
131  PAPI_L3_ICA_idx, /*L3 instruction cache accesses */
132  PAPI_L1_ICR_idx, /*L1 instruction cache reads */
133  /* 0x50 */
134  PAPI_L2_ICR_idx, /*L2 instruction cache reads */
135  PAPI_L3_ICR_idx, /*L3 instruction cache reads */
136  PAPI_L1_ICW_idx, /*L1 instruction cache writes */
137  PAPI_L2_ICW_idx, /*L2 instruction cache writes */
138  PAPI_L3_ICW_idx, /*L3 instruction cache writes */
139  PAPI_L1_TCH_idx, /*L1 total cache hits */
140  PAPI_L2_TCH_idx, /*L2 total cache hits */
141  PAPI_L3_TCH_idx, /*L3 total cache hits */
142  PAPI_L1_TCA_idx, /*L1 total cache accesses */
143  PAPI_L2_TCA_idx, /*L2 total cache accesses */
144  PAPI_L3_TCA_idx, /*L3 total cache accesses */
145  PAPI_L1_TCR_idx, /*L1 total cache reads */
146  PAPI_L2_TCR_idx, /*L2 total cache reads */
147  PAPI_L3_TCR_idx, /*L3 total cache reads */
148  PAPI_L1_TCW_idx, /*L1 total cache writes */
149  PAPI_L2_TCW_idx, /*L2 total cache writes */
150  /* 0x60 */
151  PAPI_L3_TCW_idx, /*L3 total cache writes */
152  PAPI_FML_INS_idx, /*FM ins */
153  PAPI_FAD_INS_idx, /*FA ins */
154  PAPI_FDV_INS_idx, /*FD ins */
155  PAPI_FSQ_INS_idx, /*FSq ins */
156  PAPI_FNV_INS_idx, /*Finv ins */
157  PAPI_FP_OPS_idx, /*Floating point operations executed */
158  PAPI_SP_OPS_idx, /* Floating point operations executed; optimized to count scaled single precision vector operations */
159  PAPI_DP_OPS_idx, /* Floating point operations executed; optimized to count scaled double precision vector operations */
160  PAPI_VEC_SP_idx, /* Single precision vector/SIMD instructions */
161  PAPI_VEC_DP_idx, /* Double precision vector/SIMD instructions */
162  PAPI_REF_CYC_idx, /* Reference clock cycles */
163  PAPI_END_idx /*This should always be last! */
164 };