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x86_cpuid_info.c File Reference
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Data Structures

struct  _intel_cache_info
 

Macros

#define TLB_SIZES   3 /* number of different page sizes for a single TLB descriptor */
 

Functions

static void init_mem_hierarchy (PAPI_mh_info_t *mh_info)
 
static int init_amd (PAPI_mh_info_t *mh_info, int *levels)
 
static short int _amd_L2_L3_assoc (unsigned short int pattern)
 
static int init_intel (PAPI_mh_info_t *mh_info, int *levels)
 
static void cpuid (unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
 
int _x86_cache_info (PAPI_mh_info_t *mh_info)
 
static void print_intel_cache_table ()
 
static void intel_decode_descriptor (struct _intel_cache_info *d, PAPI_mh_level_t *L)
 
static void cpuid2 (unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx, unsigned int index, unsigned int ecx_in)
 
static int init_intel_leaf4 (PAPI_mh_info_t *mh_info, int *num_levels)
 
static int init_intel_leaf2 (PAPI_mh_info_t *mh_info, int *num_levels)
 
int _x86_detect_hypervisor (char *vendor_name)
 

Variables

static struct _intel_cache_info intel_cache []
 

Macro Definition Documentation

#define TLB_SIZES   3 /* number of different page sizes for a single TLB descriptor */

Definition at line 349 of file x86_cpuid_info.c.

Function Documentation

static short int _amd_L2_L3_assoc ( unsigned short int  pattern)
static

Definition at line 105 of file x86_cpuid_info.c.

106 {
107  /* From "CPUID Specification" #25481 Rev 2.28, April 2008 */
108  short int assoc[16] =
109  { 0, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, SHRT_MAX };
110  if ( pattern > 0xF )
111  return -1;
112  return ( assoc[pattern] );
113 }
unsigned int pattern
Definition: iozone.c:1531

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int _x86_cache_info ( PAPI_mh_info_t mh_info)

Definition at line 40 of file x86_cpuid_info.c.

41 {
42  int retval = 0;
43  union
44  {
45  struct
46  {
47  unsigned int ax, bx, cx, dx;
48  } e;
49  char vendor[20]; /* leave room for terminator bytes */
50  } reg;
51 
52  /* Don't use cpu_type to determine the processor.
53  * get the information directly from the chip.
54  */
55  reg.e.ax = 0; /* function code 0: vendor string */
56  /* The vendor string is composed of EBX:EDX:ECX.
57  * by swapping the register addresses in the call below,
58  * the string is correctly composed in the char array.
59  */
60  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.dx, &reg.e.cx );
61  reg.vendor[16] = 0;
62  MEMDBG( "Vendor: %s\n", &reg.vendor[4] );
63 
64  init_mem_hierarchy( mh_info );
65 
66  if ( !strncmp( "GenuineIntel", &reg.vendor[4], 12 ) ) {
67  init_intel( mh_info, &mh_info->levels);
68  } else if ( !strncmp( "AuthenticAMD", &reg.vendor[4], 12 ) ) {
69  init_amd( mh_info, &mh_info->levels );
70  } else {
71  MEMDBG( "Unsupported cpu type; Not Intel or AMD x86\n" );
72  return PAPI_ENOIMPL;
73  }
74 
75  /* This works only because an empty cache element is initialized to 0 */
76  MEMDBG( "Detected L1: %d L2: %d L3: %d\n",
77  mh_info->level[0].cache[0].size + mh_info->level[0].cache[1].size,
78  mh_info->level[1].cache[0].size + mh_info->level[1].cache[1].size,
79  mh_info->level[2].cache[0].size + mh_info->level[2].cache[1].size );
80  return retval;
81 }
int levels
Definition: papi.h:769
#define PAPI_ENOIMPL
Definition: fpapi.h:124
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
static int init_intel(PAPI_mh_info_t *mh_info, int *levels)
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:763
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:770
static void init_mem_hierarchy(PAPI_mh_info_t *mh_info)
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
ssize_t retval
Definition: libasync.c:338
static int init_amd(PAPI_mh_info_t *mh_info, int *levels)

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int _x86_detect_hypervisor ( char *  vendor_name)

Definition at line 1491 of file x86_cpuid_info.c.

1492 {
1493  unsigned int eax, ebx, ecx, edx;
1494  char hyper_vendor_id[13];
1495 
1496  cpuid2(&eax, &ebx, &ecx, &edx,0x1,0);
1497  /* This is the hypervisor bit, ecx bit 31 */
1498  if (ecx&0x80000000) {
1499  /* There are various values in the 0x4000000X range */
1500  /* It is questionable how standard they are */
1501  /* For now we just return the name. */
1502  cpuid2(&eax, &ebx, &ecx, &edx, 0x40000000,0);
1503  memcpy(hyper_vendor_id + 0, &ebx, 4);
1504  memcpy(hyper_vendor_id + 4, &ecx, 4);
1505  memcpy(hyper_vendor_id + 8, &edx, 4);
1506  hyper_vendor_id[12] = '\0';
1507  strncpy(vendor_name,hyper_vendor_id,PAPI_MAX_STR_LEN);
1508  return 1;
1509  }
1510  else {
1511  strncpy(vendor_name,"none",PAPI_MAX_STR_LEN);
1512  }
1513  return 0;
1514 }
#define PAPI_MAX_STR_LEN
Definition: fpapi.h:43
static void cpuid2(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx, unsigned int index, unsigned int ecx_in)

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static void cpuid ( unsigned int a,
unsigned int b,
unsigned int c,
unsigned int d 
)
inlinestatic

Definition at line 26 of file x86_cpuid_info.c.

27 {
28  unsigned int op = *a;
29  // .byte 0x53 == push ebx. it's universal for 32 and 64 bit
30  // .byte 0x5b == pop ebx.
31  // Some gcc's (4.1.2 on Core2) object to pairing push/pop and ebx in 64 bit mode.
32  // Using the opcode directly avoids this problem.
33  __asm__ __volatile__( ".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b":"=a"( *a ), "=S"( *b ), "=c"( *c ),
34  "=d"
35  ( *d )
36  : "a"( op ) );
37 }
double c
Definition: multiplex.c:22
static double a[MATRIX_SIZE][MATRIX_SIZE]
Definition: rapl_basic.c:37
static double b[MATRIX_SIZE][MATRIX_SIZE]
Definition: rapl_basic.c:38
int int op
Definition: iozone.c:19389

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static void cpuid2 ( unsigned int eax,
unsigned int ebx,
unsigned int ecx,
unsigned int edx,
unsigned int  index,
unsigned int  ecx_in 
)
inlinestatic

Definition at line 1251 of file x86_cpuid_info.c.

1254 {
1255  unsigned int a,b,c,d;
1256  __asm__ __volatile__ (".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b"
1257  : "=a" (a), "=S" (b), "=c" (c), "=d" (d) \
1258  : "0" (index), "2"(ecx_in) );
1259  *eax = a; *ebx = b; *ecx = c; *edx = d;
1260 }
double c
Definition: multiplex.c:22
static double a[MATRIX_SIZE][MATRIX_SIZE]
Definition: rapl_basic.c:37
static double b[MATRIX_SIZE][MATRIX_SIZE]
Definition: rapl_basic.c:38

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static int init_amd ( PAPI_mh_info_t mh_info,
int levels 
)
static

Definition at line 117 of file x86_cpuid_info.c.

118 {
119  union
120  {
121  struct
122  {
123  unsigned int ax, bx, cx, dx;
124  } e;
125  unsigned char byt[16];
126  } reg;
127  int i, j, levels = 0;
128  PAPI_mh_level_t *L = mh_info->level;
129 
130  /*
131  * Layout of CPU information taken from :
132  * "CPUID Specification" #25481 Rev 2.28, April 2008 for most current info.
133  */
134 
135  MEMDBG( "Initializing AMD memory info\n" );
136  /* AMD level 1 cache info */
137  reg.e.ax = 0x80000005; /* extended function code 5: L1 Cache and TLB Identifiers */
138  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.cx, &reg.e.dx );
139 
140  MEMDBG( "e.ax=0x%8.8x e.bx=0x%8.8x e.cx=0x%8.8x e.dx=0x%8.8x\n",
141  reg.e.ax, reg.e.bx, reg.e.cx, reg.e.dx );
142  MEMDBG
143  ( ":\neax: %#x %#x %#x %#x\nebx: %#x %#x %#x %#x\necx: %#x %#x %#x %#x\nedx: %#x %#x %#x %#x\n",
144  reg.byt[0], reg.byt[1], reg.byt[2], reg.byt[3], reg.byt[4],
145  reg.byt[5], reg.byt[6], reg.byt[7], reg.byt[8], reg.byt[9],
146  reg.byt[10], reg.byt[11], reg.byt[12], reg.byt[13], reg.byt[14],
147  reg.byt[15] );
148 
149  /* NOTE: We assume L1 cache and TLB always exists */
150  /* L1 TLB info */
151 
152  /* 4MB memory page information; half the number of entries as 2MB */
153  L[0].tlb[0].type = PAPI_MH_TYPE_INST;
154  L[0].tlb[0].num_entries = reg.byt[0] / 2;
155  L[0].tlb[0].page_size = 4096 << 10;
156  L[0].tlb[0].associativity = reg.byt[1];
157 
158  L[0].tlb[1].type = PAPI_MH_TYPE_DATA;
159  L[0].tlb[1].num_entries = reg.byt[2] / 2;
160  L[0].tlb[1].page_size = 4096 << 10;
161  L[0].tlb[1].associativity = reg.byt[3];
162 
163  /* 2MB memory page information */
164  L[0].tlb[2].type = PAPI_MH_TYPE_INST;
165  L[0].tlb[2].num_entries = reg.byt[0];
166  L[0].tlb[2].page_size = 2048 << 10;
167  L[0].tlb[2].associativity = reg.byt[1];
168 
169  L[0].tlb[3].type = PAPI_MH_TYPE_DATA;
170  L[0].tlb[3].num_entries = reg.byt[2];
171  L[0].tlb[3].page_size = 2048 << 10;
172  L[0].tlb[3].associativity = reg.byt[3];
173 
174  /* 4k page information */
175  L[0].tlb[4].type = PAPI_MH_TYPE_INST;
176  L[0].tlb[4].num_entries = reg.byt[4];
177  L[0].tlb[4].page_size = 4 << 10;
178  L[0].tlb[4].associativity = reg.byt[5];
179 
180  L[0].tlb[5].type = PAPI_MH_TYPE_DATA;
181  L[0].tlb[5].num_entries = reg.byt[6];
182  L[0].tlb[5].page_size = 4 << 10;
183  L[0].tlb[5].associativity = reg.byt[7];
184 
185  for ( i = 0; i < PAPI_MH_MAX_LEVELS; i++ ) {
186  if ( L[0].tlb[i].associativity == 0xff )
187  L[0].tlb[i].associativity = SHRT_MAX;
188  }
189 
190  /* L1 D-cache info */
191  L[0].cache[0].type =
193  L[0].cache[0].size = reg.byt[11] << 10;
194  L[0].cache[0].associativity = reg.byt[10];
195  L[0].cache[0].line_size = reg.byt[8];
196  /* Byt[9] is "Lines per tag" */
197  /* Is that == lines per cache? */
198  /* L[0].cache[1].num_lines = reg.byt[9]; */
199  if ( L[0].cache[0].line_size )
200  L[0].cache[0].num_lines = L[0].cache[0].size / L[0].cache[0].line_size;
201  MEMDBG( "D-Cache Line Count: %d; Computed: %d\n", reg.byt[9],
202  L[0].cache[0].num_lines );
203 
204  /* L1 I-cache info */
205  L[0].cache[1].type = PAPI_MH_TYPE_INST;
206  L[0].cache[1].size = reg.byt[15] << 10;
207  L[0].cache[1].associativity = reg.byt[14];
208  L[0].cache[1].line_size = reg.byt[12];
209  /* Byt[13] is "Lines per tag" */
210  /* Is that == lines per cache? */
211  /* L[0].cache[1].num_lines = reg.byt[13]; */
212  if ( L[0].cache[1].line_size )
213  L[0].cache[1].num_lines = L[0].cache[1].size / L[0].cache[1].line_size;
214  MEMDBG( "I-Cache Line Count: %d; Computed: %d\n", reg.byt[13],
215  L[0].cache[1].num_lines );
216 
217  for ( i = 0; i < 2; i++ ) {
218  if ( L[0].cache[i].associativity == 0xff )
219  L[0].cache[i].associativity = SHRT_MAX;
220  }
221 
222  /* AMD L2/L3 Cache and L2 TLB info */
223  /* NOTE: For safety we assume L2 and L3 cache and TLB may not exist */
224 
225  reg.e.ax = 0x80000006; /* extended function code 6: L2/L3 Cache and L2 TLB Identifiers */
226  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.cx, &reg.e.dx );
227 
228  MEMDBG( "e.ax=0x%8.8x e.bx=0x%8.8x e.cx=0x%8.8x e.dx=0x%8.8x\n",
229  reg.e.ax, reg.e.bx, reg.e.cx, reg.e.dx );
230  MEMDBG
231  ( ":\neax: %#x %#x %#x %#x\nebx: %#x %#x %#x %#x\necx: %#x %#x %#x %#x\nedx: %#x %#x %#x %#x\n",
232  reg.byt[0], reg.byt[1], reg.byt[2], reg.byt[3], reg.byt[4],
233  reg.byt[5], reg.byt[6], reg.byt[7], reg.byt[8], reg.byt[9],
234  reg.byt[10], reg.byt[11], reg.byt[12], reg.byt[13], reg.byt[14],
235  reg.byt[15] );
236 
237  /* L2 TLB info */
238 
239  if ( reg.byt[0] | reg.byt[1] ) { /* Level 2 ITLB exists */
240  /* 4MB ITLB page information; half the number of entries as 2MB */
241  L[1].tlb[0].type = PAPI_MH_TYPE_INST;
242  L[1].tlb[0].num_entries =
243  ( ( ( short ) ( reg.byt[1] & 0xF ) << 8 ) + reg.byt[0] ) / 2;
244  L[1].tlb[0].page_size = 4096 << 10;
245  L[1].tlb[0].associativity =
246  _amd_L2_L3_assoc( ( reg.byt[1] & 0xF0 ) >> 4 );
247 
248  /* 2MB ITLB page information */
249  L[1].tlb[2].type = PAPI_MH_TYPE_INST;
250  L[1].tlb[2].num_entries = L[1].tlb[0].num_entries * 2;
251  L[1].tlb[2].page_size = 2048 << 10;
252  L[1].tlb[2].associativity = L[1].tlb[0].associativity;
253  }
254 
255  if ( reg.byt[2] | reg.byt[3] ) { /* Level 2 DTLB exists */
256  /* 4MB DTLB page information; half the number of entries as 2MB */
257  L[1].tlb[1].type = PAPI_MH_TYPE_DATA;
258  L[1].tlb[1].num_entries =
259  ( ( ( short ) ( reg.byt[3] & 0xF ) << 8 ) + reg.byt[2] ) / 2;
260  L[1].tlb[1].page_size = 4096 << 10;
261  L[1].tlb[1].associativity =
262  _amd_L2_L3_assoc( ( reg.byt[3] & 0xF0 ) >> 4 );
263 
264  /* 2MB DTLB page information */
265  L[1].tlb[3].type = PAPI_MH_TYPE_DATA;
266  L[1].tlb[3].num_entries = L[1].tlb[1].num_entries * 2;
267  L[1].tlb[3].page_size = 2048 << 10;
268  L[1].tlb[3].associativity = L[1].tlb[1].associativity;
269  }
270 
271  /* 4k page information */
272  if ( reg.byt[4] | reg.byt[5] ) { /* Level 2 ITLB exists */
273  L[1].tlb[4].type = PAPI_MH_TYPE_INST;
274  L[1].tlb[4].num_entries =
275  ( ( short ) ( reg.byt[5] & 0xF ) << 8 ) + reg.byt[4];
276  L[1].tlb[4].page_size = 4 << 10;
277  L[1].tlb[4].associativity =
278  _amd_L2_L3_assoc( ( reg.byt[5] & 0xF0 ) >> 4 );
279  }
280  if ( reg.byt[6] | reg.byt[7] ) { /* Level 2 DTLB exists */
281  L[1].tlb[5].type = PAPI_MH_TYPE_DATA;
282  L[1].tlb[5].num_entries =
283  ( ( short ) ( reg.byt[7] & 0xF ) << 8 ) + reg.byt[6];
284  L[1].tlb[5].page_size = 4 << 10;
285  L[1].tlb[5].associativity =
286  _amd_L2_L3_assoc( ( reg.byt[7] & 0xF0 ) >> 4 );
287  }
288 
289  /* AMD Level 2 cache info */
290  if ( reg.e.cx ) {
291  L[1].cache[0].type =
293  L[1].cache[0].size = ( int ) ( ( reg.e.cx & 0xffff0000 ) >> 6 ); /* right shift by 16; multiply by 2^10 */
294  L[1].cache[0].associativity =
295  _amd_L2_L3_assoc( ( reg.byt[9] & 0xF0 ) >> 4 );
296  L[1].cache[0].line_size = reg.byt[8];
297 /* L[1].cache[0].num_lines = reg.byt[9]&0xF; */
298  if ( L[1].cache[0].line_size )
299  L[1].cache[0].num_lines =
300  L[1].cache[0].size / L[1].cache[0].line_size;
301  MEMDBG( "U-Cache Line Count: %d; Computed: %d\n", reg.byt[9] & 0xF,
302  L[1].cache[0].num_lines );
303  }
304 
305  /* AMD Level 3 cache info (shared across cores) */
306  if ( reg.e.dx ) {
307  L[2].cache[0].type =
309  L[2].cache[0].size = ( int ) ( reg.e.dx & 0xfffc0000 ) << 1; /* in blocks of 512KB (2^19) */
310  L[2].cache[0].associativity =
311  _amd_L2_L3_assoc( ( reg.byt[13] & 0xF0 ) >> 4 );
312  L[2].cache[0].line_size = reg.byt[12];
313 /* L[2].cache[0].num_lines = reg.byt[13]&0xF; */
314  if ( L[2].cache[0].line_size )
315  L[2].cache[0].num_lines =
316  L[2].cache[0].size / L[2].cache[0].line_size;
317  MEMDBG( "U-Cache Line Count: %d; Computed: %d\n", reg.byt[13] & 0xF,
318  L[1].cache[0].num_lines );
319  }
320  for ( i = 0; i < PAPI_MAX_MEM_HIERARCHY_LEVELS; i++ ) {
321  for ( j = 0; j < PAPI_MH_MAX_LEVELS; j++ ) {
322  /* Compute the number of levels of hierarchy actually used */
323  if ( L[i].tlb[j].type != PAPI_MH_TYPE_EMPTY ||
324  L[i].cache[j].type != PAPI_MH_TYPE_EMPTY )
325  levels = i + 1;
326  }
327  }
328  *num_levels = levels;
329  return PAPI_OK;
330 }
#define PAPI_MH_TYPE_INST
Definition: papi.h:725
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
#define PAPI_MH_TYPE_WB
Definition: papi.h:732
int associativity
Definition: papi.h:748
return PAPI_OK
Definition: linux-nvml.c:458
#define PAPI_MH_TYPE_PSEUDO_LRU
Definition: papi.h:736
#define PAPI_MH_TYPE_DATA
Definition: papi.h:726
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:763
int i
Definition: fileop.c:140
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:770
PAPI_mh_tlb_info_t tlb[PAPI_MH_MAX_LEVELS]
Definition: papi.h:762
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
int
Definition: iozone.c:18528
static short int _amd_L2_L3_assoc(unsigned short int pattern)
#define PAPI_MH_TYPE_UNIFIED
Definition: papi.h:729
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:724
#define PAPI_MH_TYPE_WT
Definition: papi.h:731
long j
Definition: iozone.c:19135
#define PAPI_MH_MAX_LEVELS
Definition: fpapi.h:87
#define PAPI_MAX_MEM_HIERARCHY_LEVELS
Definition: papi.h:741

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static int init_intel ( PAPI_mh_info_t mh_info,
int levels 
)
static

Definition at line 1468 of file x86_cpuid_info.c.

1469 {
1470 
1471  int result;
1472  int num_levels;
1473 
1474  /* try using the oldest leaf2 method first */
1475  result=init_intel_leaf2(mh_info, &num_levels);
1476 
1477  if (result!=PAPI_OK) {
1478  /* All Core2 and newer also support leaf4 detection */
1479  /* Starting with Westmere *only* leaf4 is supported */
1480  result=init_intel_leaf4(mh_info, &num_levels);
1481  }
1482 
1483  *levels=num_levels;
1484  return PAPI_OK;
1485 }
static int init_intel_leaf2(PAPI_mh_info_t *mh_info, int *num_levels)
return PAPI_OK
Definition: linux-nvml.c:458
static int init_intel_leaf4(PAPI_mh_info_t *mh_info, int *num_levels)

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static int init_intel_leaf2 ( PAPI_mh_info_t mh_info,
int num_levels 
)
static

Definition at line 1373 of file x86_cpuid_info.c.

1374 {
1375  /* cpuid() returns memory copies of 4 32-bit registers
1376  * this union allows them to be accessed as either registers
1377  * or individual bytes. Remember that Intel is little-endian.
1378  */
1379  union
1380  {
1381  struct
1382  {
1383  unsigned int ax, bx, cx, dx;
1384  } e;
1385  unsigned char descrip[16];
1386  } reg;
1387 
1388  int r; /* register boundary index */
1389  int b; /* byte index into a register */
1390  int i; /* byte index into the descrip array */
1391  int t; /* table index into the static descriptor table */
1392  int count; /* how many times to call cpuid; from eax:lsb */
1393  int size; /* size of the descriptor table */
1394  int last_level = 0; /* how many levels in the cache hierarchy */
1395 
1396  int need_leaf4=0;
1397 
1398  /* All of Intel's cache info is in 1 call to cpuid
1399  * however it is a table lookup :(
1400  */
1401  MEMDBG( "Initializing Intel Cache and TLB descriptors\n" );
1402 
1403 #ifdef DEBUG
1404  if ( ISLEVEL( DEBUG_MEMORY ) )
1406 #endif
1407 
1408  reg.e.ax = 0x2; /* function code 2: cache descriptors */
1409  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.cx, &reg.e.dx );
1410 
1411  MEMDBG( "e.ax=0x%8.8x e.bx=0x%8.8x e.cx=0x%8.8x e.dx=0x%8.8x\n",
1412  reg.e.ax, reg.e.bx, reg.e.cx, reg.e.dx );
1413  MEMDBG
1414  ( ":\nd0: %#x %#x %#x %#x\nd1: %#x %#x %#x %#x\nd2: %#x %#x %#x %#x\nd3: %#x %#x %#x %#x\n",
1415  reg.descrip[0], reg.descrip[1], reg.descrip[2], reg.descrip[3],
1416  reg.descrip[4], reg.descrip[5], reg.descrip[6], reg.descrip[7],
1417  reg.descrip[8], reg.descrip[9], reg.descrip[10], reg.descrip[11],
1418  reg.descrip[12], reg.descrip[13], reg.descrip[14], reg.descrip[15] );
1419 
1420  count = reg.descrip[0]; /* # times to repeat CPUID call. Not implemented. */
1421 
1422  /* Knights Corner at least returns 0 here */
1423  if (count==0) goto early_exit;
1424 
1425  size = ( sizeof ( intel_cache ) / sizeof ( struct _intel_cache_info ) ); /* # descriptors */
1426  MEMDBG( "Repeat cpuid(2,...) %d times. If not 1, code is broken.\n",
1427  count );
1428  if (count!=1) {
1429  fprintf(stderr,"Warning: Unhandled cpuid count of %d\n",count);
1430  }
1431 
1432  for ( r = 0; r < 4; r++ ) { /* walk the registers */
1433  if ( ( reg.descrip[r * 4 + 3] & 0x80 ) == 0 ) { /* only process if high order bit is 0 */
1434  for ( b = 3; b >= 0; b-- ) { /* walk the descriptor bytes from high to low */
1435  i = r * 4 + b; /* calculate an index into the array of descriptors */
1436  if ( i ) { /* skip the low order byte in eax [0]; it's the count (see above) */
1437  if ( reg.descrip[i] == 0xff ) {
1438  MEMDBG("Warning! PAPI x86_cache: must implement cpuid leaf 4\n");
1439  need_leaf4=1;
1440  return PAPI_ENOSUPP;
1441  /* we might continue instead */
1442  /* in order to get TLB info */
1443  /* continue; */
1444  }
1445  for ( t = 0; t < size; t++ ) { /* walk the descriptor table */
1446  if ( reg.descrip[i] == intel_cache[t].descriptor ) { /* find match */
1447  if ( intel_cache[t].level > last_level )
1448  last_level = intel_cache[t].level;
1450  mh_info->level );
1451  }
1452  }
1453  }
1454  }
1455  }
1456  }
1457 early_exit:
1458  MEMDBG( "# of Levels: %d\n", last_level );
1459  *num_levels=last_level;
1460  if (need_leaf4) {
1461  return PAPI_ENOSUPP;
1462  }
1463  return PAPI_OK;
1464 }
static void intel_decode_descriptor(struct _intel_cache_info *d, PAPI_mh_level_t *L)
static void print_intel_cache_table()
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
static struct _intel_cache_info intel_cache[]
return PAPI_OK
Definition: linux-nvml.c:458
int count
Definition: iozone.c:22422
#define DEBUG_MEMORY
Definition: papi_debug.h:34
t
Definition: iozone.c:23562
int i
Definition: fileop.c:140
#define PAPI_ENOSUPP
Definition: fpapi.h:123
char *long long size
Definition: iozone.c:12023
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:770
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
static double b[MATRIX_SIZE][MATRIX_SIZE]
Definition: rapl_basic.c:38
#define ISLEVEL(a)
Definition: papi_debug.h:54

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static int init_intel_leaf4 ( PAPI_mh_info_t mh_info,
int num_levels 
)
static

Definition at line 1264 of file x86_cpuid_info.c.

1265 {
1266 
1267  unsigned int eax, ebx, ecx, edx;
1268  unsigned int maxidx, ecx_in;
1269  int next;
1270 
1271  int cache_type,cache_level,cache_selfinit,cache_fullyassoc;
1272  int cache_linesize,cache_partitions,cache_ways,cache_sets;
1273 
1275 
1276  *num_levels=0;
1277 
1278  cpuid2(&eax,&ebx,&ecx,&edx, 0, 0);
1279  maxidx = eax;
1280 
1281  if (maxidx<4) {
1282  MEMDBG("Warning! CPUID Index 4 not supported!\n");
1283  return PAPI_ENOSUPP;
1284  }
1285 
1286  ecx_in=0;
1287  while(1) {
1288  cpuid2(&eax,&ebx,&ecx,&edx, 4, ecx_in);
1289 
1290 
1291 
1292  /* decoded as per table 3-12 in Intel Software Developer's Manual Volume 2A */
1293 
1294  cache_type=eax&0x1f;
1295  if (cache_type==0) break;
1296 
1297  cache_level=(eax>>5)&0x3;
1298  cache_selfinit=(eax>>8)&0x1;
1299  cache_fullyassoc=(eax>>9)&0x1;
1300 
1301  cache_linesize=(ebx&0xfff)+1;
1302  cache_partitions=((ebx>>12)&0x3ff)+1;
1303  cache_ways=((ebx>>22)&0x3ff)+1;
1304 
1305  cache_sets=(ecx)+1;
1306 
1307  /* should we export this info?
1308 
1309  cache_maxshare=((eax>>14)&0xfff)+1;
1310  cache_maxpackage=((eax>>26)&0x3f)+1;
1311 
1312  cache_wb=(edx)&1;
1313  cache_inclusive=(edx>>1)&1;
1314  cache_indexing=(edx>>2)&1;
1315  */
1316 
1317  if (cache_level>*num_levels) *num_levels=cache_level;
1318 
1319  /* find next slot available to hold cache info */
1320  for ( next = 0; next < PAPI_MH_MAX_LEVELS - 1; next++ ) {
1321  if ( mh_info->level[cache_level-1].cache[next].type == PAPI_MH_TYPE_EMPTY ) break;
1322  }
1323 
1324  c=&(mh_info->level[cache_level-1].cache[next]);
1325 
1326  switch(cache_type) {
1327  case 1: MEMDBG("L%d Data Cache\n",cache_level);
1329  break;
1330  case 2: MEMDBG("L%d Instruction Cache\n",cache_level);
1332  break;
1333  case 3: MEMDBG("L%d Unified Cache\n",cache_level);
1335  break;
1336  }
1337 
1338  if (cache_selfinit) { MEMDBG("\tSelf-init\n"); }
1339  if (cache_fullyassoc) { MEMDBG("\tFully Associtative\n"); }
1340 
1341  //MEMDBG("\tMax logical processors sharing cache: %d\n",cache_maxshare);
1342  //MEMDBG("\tMax logical processors sharing package: %d\n",cache_maxpackage);
1343 
1344  MEMDBG("\tCache linesize: %d\n",cache_linesize);
1345 
1346  MEMDBG("\tCache partitions: %d\n",cache_partitions);
1347  MEMDBG("\tCache associaticity: %d\n",cache_ways);
1348 
1349  MEMDBG("\tCache sets: %d\n",cache_sets);
1350  MEMDBG("\tCache size = %dkB\n",
1351  (cache_ways*cache_partitions*cache_linesize*cache_sets)/1024);
1352 
1353  //MEMDBG("\tWBINVD/INVD acts on lower caches: %d\n",cache_wb);
1354  //MEMDBG("\tCache is not inclusive: %d\n",cache_inclusive);
1355  //MEMDBG("\tComplex cache indexing: %d\n",cache_indexing);
1356 
1357  c->line_size=cache_linesize;
1358  if (cache_fullyassoc) {
1359  c->associativity=SHRT_MAX;
1360  }
1361  else {
1362  c->associativity=cache_ways;
1363  }
1364  c->size=(cache_ways*cache_partitions*cache_linesize*cache_sets);
1365  c->num_lines=cache_ways*cache_partitions*cache_sets;
1366 
1367  ecx_in++;
1368  }
1369  return PAPI_OK;
1370 }
#define PAPI_MH_TYPE_INST
Definition: papi.h:725
static void cpuid2(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx, unsigned int index, unsigned int ecx_in)
return PAPI_OK
Definition: linux-nvml.c:458
double c
Definition: multiplex.c:22
#define PAPI_MH_TYPE_DATA
Definition: papi.h:726
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:763
#define PAPI_ENOSUPP
Definition: fpapi.h:123
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:770
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
nsize_list next
Definition: iozone.c:20053
#define PAPI_MH_TYPE_UNIFIED
Definition: papi.h:729
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:724
#define PAPI_MH_MAX_LEVELS
Definition: fpapi.h:87

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static void init_mem_hierarchy ( PAPI_mh_info_t mh_info)
static

Definition at line 84 of file x86_cpuid_info.c.

85 {
86  int i, j;
87  PAPI_mh_level_t *L = mh_info->level;
88 
89  /* initialize entire memory hierarchy structure to benign values */
90  for ( i = 0; i < PAPI_MAX_MEM_HIERARCHY_LEVELS; i++ ) {
91  for ( j = 0; j < PAPI_MH_MAX_LEVELS; j++ ) {
93  L[i].tlb[j].num_entries = 0;
94  L[i].tlb[j].associativity = 0;
96  L[i].cache[j].size = 0;
97  L[i].cache[j].line_size = 0;
98  L[i].cache[j].num_lines = 0;
99  L[i].cache[j].associativity = 0;
100  }
101  }
102 }
int associativity
Definition: papi.h:748
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:763
int i
Definition: fileop.c:140
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:770
PAPI_mh_tlb_info_t tlb[PAPI_MH_MAX_LEVELS]
Definition: papi.h:762
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:724
long j
Definition: iozone.c:19135
#define PAPI_MH_MAX_LEVELS
Definition: fpapi.h:87
#define PAPI_MAX_MEM_HIERARCHY_LEVELS
Definition: papi.h:741

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static void intel_decode_descriptor ( struct _intel_cache_info d,
PAPI_mh_level_t L 
)
static

Definition at line 1200 of file x86_cpuid_info.c.

1201 {
1202  int i, next;
1203  int level = d->level - 1;
1206 
1207  if ( d->descriptor == 0x49 ) { /* special case */
1208  unsigned int r_eax, r_ebx, r_ecx, r_edx;
1209  r_eax = 0x1; /* function code 1: family & model */
1210  cpuid( &r_eax, &r_ebx, &r_ecx, &r_edx );
1211  /* override table for Family F, model 6 only */
1212  if ( ( r_eax & 0x0FFF3FF0 ) == 0xF60 )
1213  level = 3;
1214  }
1215  if ( d->type & PAPI_MH_TYPE_TLB ) {
1216  for ( next = 0; next < PAPI_MH_MAX_LEVELS - 1; next++ ) {
1217  if ( L[level].tlb[next].type == PAPI_MH_TYPE_EMPTY )
1218  break;
1219  }
1220  /* expand TLB entries for multiple possible page sizes */
1221  for ( i = 0; i < TLB_SIZES && next < PAPI_MH_MAX_LEVELS && d->size[i];
1222  i++, next++ ) {
1223 // printf("Level %d Descriptor: %#x TLB type %#x next: %d, i: %d\n", level, d->descriptor, d->type, next, i);
1224  t = &L[level].tlb[next];
1225  t->type = PAPI_MH_CACHE_TYPE( d->type );
1226  t->num_entries = d->entries;
1227  t->page_size = d->size[i] << 10; /* minimum page size in KB */
1228  t->associativity = d->associativity;
1229  /* another special case */
1230  if ( d->descriptor == 0xB1 && d->size[i] == 4096 )
1231  t->num_entries = d->entries / 2;
1232  }
1233  } else {
1234  for ( next = 0; next < PAPI_MH_MAX_LEVELS - 1; next++ ) {
1235  if ( L[level].cache[next].type == PAPI_MH_TYPE_EMPTY )
1236  break;
1237  }
1238 // printf("Level %d Descriptor: %#x Cache type %#x next: %d\n", level, d->descriptor, d->type, next);
1239  c = &L[level].cache[next];
1240  c->type = PAPI_MH_CACHE_TYPE( d->type );
1241  c->size = d->size[0] << 10; /* convert from KB to bytes */
1242  c->associativity = d->associativity;
1243  if ( d->line_size ) {
1244  c->line_size = d->line_size;
1245  c->num_lines = c->size / c->line_size;
1246  }
1247  }
1248 }
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
int size[TLB_SIZES]
int associativity
Definition: papi.h:748
double c
Definition: multiplex.c:22
#define PAPI_MH_TYPE_TLB
Definition: papi.h:738
t
Definition: iozone.c:23562
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:763
int i
Definition: fileop.c:140
#define TLB_SIZES
PAPI_mh_tlb_info_t tlb[PAPI_MH_MAX_LEVELS]
Definition: papi.h:762
nsize_list next
Definition: iozone.c:20053
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:724
#define PAPI_MH_MAX_LEVELS
Definition: fpapi.h:87
#define PAPI_MH_CACHE_TYPE(a)
Definition: papi.h:730

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static void print_intel_cache_table ( )
static

Definition at line 1173 of file x86_cpuid_info.c.

1174 {
1175  int i, j, k =
1176  ( int ) ( sizeof ( intel_cache ) /
1177  sizeof ( struct _intel_cache_info ) );
1178  for ( i = 0; i < k; i++ ) {
1179  printf( "%d.\tDescriptor: %#x\n", i, intel_cache[i].descriptor );
1180  printf( "\t Level: %d\n", intel_cache[i].level );
1181  printf( "\t Type: %d\n", intel_cache[i].type );
1182  printf( "\t Size(s): " );
1183  for ( j = 0; j < TLB_SIZES; j++ )
1184  printf( "%d, ", intel_cache[i].size[j] );
1185  printf( "\n" );
1186  printf( "\t Assoc: %d\n", intel_cache[i].associativity );
1187  printf( "\t Sector: %d\n", intel_cache[i].sector );
1188  printf( "\t Line Size: %d\n", intel_cache[i].line_size );
1189  printf( "\t Entries: %d\n", intel_cache[i].entries );
1190  printf( "\n" );
1191  }
1192 }
static struct _intel_cache_info intel_cache[]
#define printf
Definition: papi_test.h:125
int i
Definition: fileop.c:140
char *long long size
Definition: iozone.c:12023
#define TLB_SIZES
int k
Definition: iozone.c:19136
int
Definition: iozone.c:18528
long j
Definition: iozone.c:19135

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Variable Documentation

struct _intel_cache_info intel_cache[]
static

Definition at line 362 of file x86_cpuid_info.c.