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x86_cpuid_info.c File Reference
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Data Structures

struct  _intel_cache_info
 

Macros

#define TLB_SIZES   3 /* number of different page sizes for a single TLB descriptor */
 

Functions

static void init_mem_hierarchy (PAPI_mh_info_t *mh_info)
 
static int init_amd (PAPI_mh_info_t *mh_info, int *levels)
 
static short int _amd_L2_L3_assoc (unsigned short int pattern)
 
static int init_intel (PAPI_mh_info_t *mh_info, int *levels)
 
static void cpuid (unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
 
int _x86_cache_info (PAPI_mh_info_t *mh_info)
 
static void print_intel_cache_table ()
 
static void intel_decode_descriptor (struct _intel_cache_info *d, PAPI_mh_level_t *L)
 
static void cpuid2 (unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx, unsigned int index, unsigned int ecx_in)
 
static int init_intel_leaf4 (PAPI_mh_info_t *mh_info, int *num_levels)
 
static int init_intel_leaf2 (PAPI_mh_info_t *mh_info, int *num_levels)
 
int _x86_detect_hypervisor (char *vendor_name)
 

Variables

static struct _intel_cache_info intel_cache []
 

Macro Definition Documentation

#define TLB_SIZES   3 /* number of different page sizes for a single TLB descriptor */

Definition at line 359 of file x86_cpuid_info.c.

Function Documentation

static short int _amd_L2_L3_assoc ( unsigned short int  pattern)
static

Definition at line 115 of file x86_cpuid_info.c.

116 {
117  /* From "CPUID Specification" #25481 Rev 2.28, April 2008 */
118  short int assoc[16] =
119  { 0, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, SHRT_MAX };
120  if ( pattern > 0xF )
121  return -1;
122  return ( assoc[pattern] );
123 }
unsigned int pattern
Definition: iozone.c:1531

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int _x86_cache_info ( PAPI_mh_info_t mh_info)

Definition at line 50 of file x86_cpuid_info.c.

51 {
52  int retval = 0;
53  union
54  {
55  struct
56  {
57  unsigned int ax, bx, cx, dx;
58  } e;
59  char vendor[20]; /* leave room for terminator bytes */
60  } reg;
61 
62  /* Don't use cpu_type to determine the processor.
63  * get the information directly from the chip.
64  */
65  reg.e.ax = 0; /* function code 0: vendor string */
66  /* The vendor string is composed of EBX:EDX:ECX.
67  * by swapping the register addresses in the call below,
68  * the string is correctly composed in the char array.
69  */
70  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.dx, &reg.e.cx );
71  reg.vendor[16] = 0;
72  MEMDBG( "Vendor: %s\n", &reg.vendor[4] );
73 
74  init_mem_hierarchy( mh_info );
75 
76  if ( !strncmp( "GenuineIntel", &reg.vendor[4], 12 ) ) {
77  init_intel( mh_info, &mh_info->levels);
78  } else if ( !strncmp( "AuthenticAMD", &reg.vendor[4], 12 ) ) {
79  init_amd( mh_info, &mh_info->levels );
80  } else {
81  MEMDBG( "Unsupported cpu type; Not Intel or AMD x86\n" );
82  return PAPI_ENOIMPL;
83  }
84 
85  /* This works only because an empty cache element is initialized to 0 */
86  MEMDBG( "Detected L1: %d L2: %d L3: %d\n",
87  mh_info->level[0].cache[0].size + mh_info->level[0].cache[1].size,
88  mh_info->level[1].cache[0].size + mh_info->level[1].cache[1].size,
89  mh_info->level[2].cache[0].size + mh_info->level[2].cache[1].size );
90  return retval;
91 }
int levels
Definition: papi.h:774
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
static int init_intel(PAPI_mh_info_t *mh_info, int *levels)
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:768
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:775
static void init_mem_hierarchy(PAPI_mh_info_t *mh_info)
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
#define PAPI_ENOIMPL
Definition: papi.h:272
ssize_t retval
Definition: libasync.c:338
static int init_amd(PAPI_mh_info_t *mh_info, int *levels)

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int _x86_detect_hypervisor ( char *  vendor_name)

Definition at line 1507 of file x86_cpuid_info.c.

1508 {
1509  unsigned int eax, ebx, ecx, edx;
1510  char hyper_vendor_id[13];
1511 
1512  cpuid2(&eax, &ebx, &ecx, &edx,0x1,0);
1513  /* This is the hypervisor bit, ecx bit 31 */
1514  if (ecx&0x80000000) {
1515  /* There are various values in the 0x4000000X range */
1516  /* It is questionable how standard they are */
1517  /* For now we just return the name. */
1518  cpuid2(&eax, &ebx, &ecx, &edx, 0x40000000,0);
1519  memcpy(hyper_vendor_id + 0, &ebx, 4);
1520  memcpy(hyper_vendor_id + 4, &ecx, 4);
1521  memcpy(hyper_vendor_id + 8, &edx, 4);
1522  hyper_vendor_id[12] = '\0';
1523  strncpy(vendor_name,hyper_vendor_id,PAPI_MAX_STR_LEN);
1524  return 1;
1525  }
1526  else {
1527  strncpy(vendor_name,"none",PAPI_MAX_STR_LEN);
1528  }
1529  return 0;
1530 }
static void cpuid2(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx, unsigned int index, unsigned int ecx_in)
#define PAPI_MAX_STR_LEN
Definition: papi.h:465

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static void cpuid ( unsigned int a,
unsigned int b,
unsigned int c,
unsigned int d 
)
inlinestatic

Definition at line 35 of file x86_cpuid_info.c.

36 {
37  unsigned int op = *a;
38  // .byte 0x53 == push ebx. it's universal for 32 and 64 bit
39  // .byte 0x5b == pop ebx.
40  // Some gcc's (4.1.2 on Core2) object to pairing push/pop and ebx in 64 bit mode.
41  // Using the opcode directly avoids this problem.
42  __asm__ __volatile__( ".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b":"=a"( *a ), "=S"( *b ), "=c"( *c ),
43  "=d"
44  ( *d )
45  : "a"( op ) );
46 }
double c
Definition: multiplex.c:22
static double b[MATRIX_SIZE][MATRIX_SIZE]
Definition: libmsr_basic.c:39
static double a[MATRIX_SIZE][MATRIX_SIZE]
Definition: libmsr_basic.c:38
int int op
Definition: iozone.c:19389

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static void cpuid2 ( unsigned int eax,
unsigned int ebx,
unsigned int ecx,
unsigned int edx,
unsigned int  index,
unsigned int  ecx_in 
)
inlinestatic

Definition at line 1272 of file x86_cpuid_info.c.

1275 {
1276  unsigned int a,b,c,d;
1277  __asm__ __volatile__ (".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b"
1278  : "=a" (a), "=S" (b), "=c" (c), "=d" (d) \
1279  : "0" (index), "2"(ecx_in) );
1280  *eax = a; *ebx = b; *ecx = c; *edx = d;
1281 }
double c
Definition: multiplex.c:22
static double b[MATRIX_SIZE][MATRIX_SIZE]
Definition: libmsr_basic.c:39
static double a[MATRIX_SIZE][MATRIX_SIZE]
Definition: libmsr_basic.c:38

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static int init_amd ( PAPI_mh_info_t mh_info,
int levels 
)
static

Definition at line 127 of file x86_cpuid_info.c.

128 {
129  union
130  {
131  struct
132  {
133  unsigned int ax, bx, cx, dx;
134  } e;
135  unsigned char byt[16];
136  } reg;
137  int i, j, levels = 0;
138  PAPI_mh_level_t *L = mh_info->level;
139 
140  /*
141  * Layout of CPU information taken from :
142  * "CPUID Specification" #25481 Rev 2.28, April 2008 for most current info.
143  */
144 
145  MEMDBG( "Initializing AMD memory info\n" );
146  /* AMD level 1 cache info */
147  reg.e.ax = 0x80000005; /* extended function code 5: L1 Cache and TLB Identifiers */
148  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.cx, &reg.e.dx );
149 
150  MEMDBG( "e.ax=%#8.8x e.bx=%#8.8x e.cx=%#8.8x e.dx=%#8.8x\n",
151  reg.e.ax, reg.e.bx, reg.e.cx, reg.e.dx );
152  MEMDBG
153  ( ":\neax: %#x %#x %#x %#x\nebx: %#x %#x %#x %#x\necx: %#x %#x %#x %#x\nedx: %#x %#x %#x %#x\n",
154  reg.byt[0], reg.byt[1], reg.byt[2], reg.byt[3], reg.byt[4],
155  reg.byt[5], reg.byt[6], reg.byt[7], reg.byt[8], reg.byt[9],
156  reg.byt[10], reg.byt[11], reg.byt[12], reg.byt[13], reg.byt[14],
157  reg.byt[15] );
158 
159  /* NOTE: We assume L1 cache and TLB always exists */
160  /* L1 TLB info */
161 
162  /* 4MB memory page information; half the number of entries as 2MB */
163  L[0].tlb[0].type = PAPI_MH_TYPE_INST;
164  L[0].tlb[0].num_entries = reg.byt[0] / 2;
165  L[0].tlb[0].page_size = 4096 << 10;
166  L[0].tlb[0].associativity = reg.byt[1];
167 
168  L[0].tlb[1].type = PAPI_MH_TYPE_DATA;
169  L[0].tlb[1].num_entries = reg.byt[2] / 2;
170  L[0].tlb[1].page_size = 4096 << 10;
171  L[0].tlb[1].associativity = reg.byt[3];
172 
173  /* 2MB memory page information */
174  L[0].tlb[2].type = PAPI_MH_TYPE_INST;
175  L[0].tlb[2].num_entries = reg.byt[0];
176  L[0].tlb[2].page_size = 2048 << 10;
177  L[0].tlb[2].associativity = reg.byt[1];
178 
179  L[0].tlb[3].type = PAPI_MH_TYPE_DATA;
180  L[0].tlb[3].num_entries = reg.byt[2];
181  L[0].tlb[3].page_size = 2048 << 10;
182  L[0].tlb[3].associativity = reg.byt[3];
183 
184  /* 4k page information */
185  L[0].tlb[4].type = PAPI_MH_TYPE_INST;
186  L[0].tlb[4].num_entries = reg.byt[4];
187  L[0].tlb[4].page_size = 4 << 10;
188  L[0].tlb[4].associativity = reg.byt[5];
189 
190  L[0].tlb[5].type = PAPI_MH_TYPE_DATA;
191  L[0].tlb[5].num_entries = reg.byt[6];
192  L[0].tlb[5].page_size = 4 << 10;
193  L[0].tlb[5].associativity = reg.byt[7];
194 
195  for ( i = 0; i < PAPI_MH_MAX_LEVELS; i++ ) {
196  if ( L[0].tlb[i].associativity == 0xff )
197  L[0].tlb[i].associativity = SHRT_MAX;
198  }
199 
200  /* L1 D-cache info */
201  L[0].cache[0].type =
203  L[0].cache[0].size = reg.byt[11] << 10;
204  L[0].cache[0].associativity = reg.byt[10];
205  L[0].cache[0].line_size = reg.byt[8];
206  /* Byt[9] is "Lines per tag" */
207  /* Is that == lines per cache? */
208  /* L[0].cache[1].num_lines = reg.byt[9]; */
209  if ( L[0].cache[0].line_size )
210  L[0].cache[0].num_lines = L[0].cache[0].size / L[0].cache[0].line_size;
211  MEMDBG( "D-Cache Line Count: %d; Computed: %d\n", reg.byt[9],
212  L[0].cache[0].num_lines );
213 
214  /* L1 I-cache info */
215  L[0].cache[1].type = PAPI_MH_TYPE_INST;
216  L[0].cache[1].size = reg.byt[15] << 10;
217  L[0].cache[1].associativity = reg.byt[14];
218  L[0].cache[1].line_size = reg.byt[12];
219  /* Byt[13] is "Lines per tag" */
220  /* Is that == lines per cache? */
221  /* L[0].cache[1].num_lines = reg.byt[13]; */
222  if ( L[0].cache[1].line_size )
223  L[0].cache[1].num_lines = L[0].cache[1].size / L[0].cache[1].line_size;
224  MEMDBG( "I-Cache Line Count: %d; Computed: %d\n", reg.byt[13],
225  L[0].cache[1].num_lines );
226 
227  for ( i = 0; i < 2; i++ ) {
228  if ( L[0].cache[i].associativity == 0xff )
229  L[0].cache[i].associativity = SHRT_MAX;
230  }
231 
232  /* AMD L2/L3 Cache and L2 TLB info */
233  /* NOTE: For safety we assume L2 and L3 cache and TLB may not exist */
234 
235  reg.e.ax = 0x80000006; /* extended function code 6: L2/L3 Cache and L2 TLB Identifiers */
236  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.cx, &reg.e.dx );
237 
238  MEMDBG( "e.ax=%#8.8x e.bx=%#8.8x e.cx=%#8.8x e.dx=%#8.8x\n",
239  reg.e.ax, reg.e.bx, reg.e.cx, reg.e.dx );
240  MEMDBG
241  ( ":\neax: %#x %#x %#x %#x\nebx: %#x %#x %#x %#x\necx: %#x %#x %#x %#x\nedx: %#x %#x %#x %#x\n",
242  reg.byt[0], reg.byt[1], reg.byt[2], reg.byt[3], reg.byt[4],
243  reg.byt[5], reg.byt[6], reg.byt[7], reg.byt[8], reg.byt[9],
244  reg.byt[10], reg.byt[11], reg.byt[12], reg.byt[13], reg.byt[14],
245  reg.byt[15] );
246 
247  /* L2 TLB info */
248 
249  if ( reg.byt[0] | reg.byt[1] ) { /* Level 2 ITLB exists */
250  /* 4MB ITLB page information; half the number of entries as 2MB */
251  L[1].tlb[0].type = PAPI_MH_TYPE_INST;
252  L[1].tlb[0].num_entries =
253  ( ( ( short ) ( reg.byt[1] & 0xF ) << 8 ) + reg.byt[0] ) / 2;
254  L[1].tlb[0].page_size = 4096 << 10;
255  L[1].tlb[0].associativity =
256  _amd_L2_L3_assoc( ( reg.byt[1] & 0xF0 ) >> 4 );
257 
258  /* 2MB ITLB page information */
259  L[1].tlb[2].type = PAPI_MH_TYPE_INST;
260  L[1].tlb[2].num_entries = L[1].tlb[0].num_entries * 2;
261  L[1].tlb[2].page_size = 2048 << 10;
262  L[1].tlb[2].associativity = L[1].tlb[0].associativity;
263  }
264 
265  if ( reg.byt[2] | reg.byt[3] ) { /* Level 2 DTLB exists */
266  /* 4MB DTLB page information; half the number of entries as 2MB */
267  L[1].tlb[1].type = PAPI_MH_TYPE_DATA;
268  L[1].tlb[1].num_entries =
269  ( ( ( short ) ( reg.byt[3] & 0xF ) << 8 ) + reg.byt[2] ) / 2;
270  L[1].tlb[1].page_size = 4096 << 10;
271  L[1].tlb[1].associativity =
272  _amd_L2_L3_assoc( ( reg.byt[3] & 0xF0 ) >> 4 );
273 
274  /* 2MB DTLB page information */
275  L[1].tlb[3].type = PAPI_MH_TYPE_DATA;
276  L[1].tlb[3].num_entries = L[1].tlb[1].num_entries * 2;
277  L[1].tlb[3].page_size = 2048 << 10;
278  L[1].tlb[3].associativity = L[1].tlb[1].associativity;
279  }
280 
281  /* 4k page information */
282  if ( reg.byt[4] | reg.byt[5] ) { /* Level 2 ITLB exists */
283  L[1].tlb[4].type = PAPI_MH_TYPE_INST;
284  L[1].tlb[4].num_entries =
285  ( ( short ) ( reg.byt[5] & 0xF ) << 8 ) + reg.byt[4];
286  L[1].tlb[4].page_size = 4 << 10;
287  L[1].tlb[4].associativity =
288  _amd_L2_L3_assoc( ( reg.byt[5] & 0xF0 ) >> 4 );
289  }
290  if ( reg.byt[6] | reg.byt[7] ) { /* Level 2 DTLB exists */
291  L[1].tlb[5].type = PAPI_MH_TYPE_DATA;
292  L[1].tlb[5].num_entries =
293  ( ( short ) ( reg.byt[7] & 0xF ) << 8 ) + reg.byt[6];
294  L[1].tlb[5].page_size = 4 << 10;
295  L[1].tlb[5].associativity =
296  _amd_L2_L3_assoc( ( reg.byt[7] & 0xF0 ) >> 4 );
297  }
298 
299  /* AMD Level 2 cache info */
300  if ( reg.e.cx ) {
301  L[1].cache[0].type =
303  L[1].cache[0].size = ( int ) ( ( reg.e.cx & 0xffff0000 ) >> 6 ); /* right shift by 16; multiply by 2^10 */
304  L[1].cache[0].associativity =
305  _amd_L2_L3_assoc( ( reg.byt[9] & 0xF0 ) >> 4 );
306  L[1].cache[0].line_size = reg.byt[8];
307 /* L[1].cache[0].num_lines = reg.byt[9]&0xF; */
308  if ( L[1].cache[0].line_size )
309  L[1].cache[0].num_lines =
310  L[1].cache[0].size / L[1].cache[0].line_size;
311  MEMDBG( "U-Cache Line Count: %d; Computed: %d\n", reg.byt[9] & 0xF,
312  L[1].cache[0].num_lines );
313  }
314 
315  /* AMD Level 3 cache info (shared across cores) */
316  if ( reg.e.dx ) {
317  L[2].cache[0].type =
319  L[2].cache[0].size = ( int ) ( reg.e.dx & 0xfffc0000 ) << 1; /* in blocks of 512KB (2^19) */
320  L[2].cache[0].associativity =
321  _amd_L2_L3_assoc( ( reg.byt[13] & 0xF0 ) >> 4 );
322  L[2].cache[0].line_size = reg.byt[12];
323 /* L[2].cache[0].num_lines = reg.byt[13]&0xF; */
324  if ( L[2].cache[0].line_size )
325  L[2].cache[0].num_lines =
326  L[2].cache[0].size / L[2].cache[0].line_size;
327  MEMDBG( "U-Cache Line Count: %d; Computed: %d\n", reg.byt[13] & 0xF,
328  L[1].cache[0].num_lines );
329  }
330  for ( i = 0; i < PAPI_MAX_MEM_HIERARCHY_LEVELS; i++ ) {
331  for ( j = 0; j < PAPI_MH_MAX_LEVELS; j++ ) {
332  /* Compute the number of levels of hierarchy actually used */
333  if ( L[i].tlb[j].type != PAPI_MH_TYPE_EMPTY ||
334  L[i].cache[j].type != PAPI_MH_TYPE_EMPTY )
335  levels = i + 1;
336  }
337  }
338  *num_levels = levels;
339  return PAPI_OK;
340 }
#define PAPI_MH_TYPE_INST
Definition: papi.h:730
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
#define PAPI_MH_TYPE_WB
Definition: papi.h:737
int associativity
Definition: papi.h:753
return PAPI_OK
Definition: linux-nvml.c:497
#define PAPI_MH_TYPE_PSEUDO_LRU
Definition: papi.h:741
#define PAPI_MH_TYPE_DATA
Definition: papi.h:731
#define PAPI_MH_MAX_LEVELS
Definition: papi.h:745
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:768
int i
Definition: fileop.c:140
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:775
PAPI_mh_tlb_info_t tlb[PAPI_MH_MAX_LEVELS]
Definition: papi.h:767
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
int
Definition: iozone.c:18528
static short int _amd_L2_L3_assoc(unsigned short int pattern)
#define PAPI_MH_TYPE_UNIFIED
Definition: papi.h:734
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:729
#define PAPI_MH_TYPE_WT
Definition: papi.h:736
long j
Definition: iozone.c:19135
#define PAPI_MAX_MEM_HIERARCHY_LEVELS
Definition: papi.h:746

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static int init_intel ( PAPI_mh_info_t mh_info,
int levels 
)
static

Definition at line 1484 of file x86_cpuid_info.c.

1485 {
1486 
1487  int result;
1488  int num_levels;
1489 
1490  /* try using the oldest leaf2 method first */
1491  result=init_intel_leaf2(mh_info, &num_levels);
1492 
1493  if (result!=PAPI_OK) {
1494  /* All Core2 and newer also support leaf4 detection */
1495  /* Starting with Westmere *only* leaf4 is supported */
1496  result=init_intel_leaf4(mh_info, &num_levels);
1497  }
1498 
1499  *levels=num_levels;
1500  return PAPI_OK;
1501 }
static int init_intel_leaf2(PAPI_mh_info_t *mh_info, int *num_levels)
return PAPI_OK
Definition: linux-nvml.c:497
static int init_intel_leaf4(PAPI_mh_info_t *mh_info, int *num_levels)

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static int init_intel_leaf2 ( PAPI_mh_info_t mh_info,
int num_levels 
)
static

Definition at line 1395 of file x86_cpuid_info.c.

1396 {
1397  /* cpuid() returns memory copies of 4 32-bit registers
1398  * this union allows them to be accessed as either registers
1399  * or individual bytes. Remember that Intel is little-endian.
1400  */
1401  union
1402  {
1403  struct
1404  {
1405  unsigned int ax, bx, cx, dx;
1406  } e;
1407  unsigned char descrip[16];
1408  } reg;
1409 
1410  int r; /* register boundary index */
1411  int b; /* byte index into a register */
1412  int i; /* byte index into the descrip array */
1413  int t; /* table index into the static descriptor table */
1414  int count; /* how many times to call cpuid; from eax:lsb */
1415  int size; /* size of the descriptor table */
1416  int last_level = 0; /* how many levels in the cache hierarchy */
1417 
1418  /* All of Intel's cache info is in 1 call to cpuid
1419  * however it is a table lookup :(
1420  */
1421  MEMDBG( "Initializing Intel Cache and TLB descriptors\n" );
1422 
1423 #ifdef DEBUG
1424  if ( ISLEVEL( DEBUG_MEMORY ) )
1426 #endif
1427 
1428  reg.e.ax = 0x2; /* function code 2: cache descriptors */
1429  cpuid( &reg.e.ax, &reg.e.bx, &reg.e.cx, &reg.e.dx );
1430 
1431  MEMDBG( "e.ax=%#8.8x e.bx=%#8.8x e.cx=%#8.8x e.dx=%#8.8x\n",
1432  reg.e.ax, reg.e.bx, reg.e.cx, reg.e.dx );
1433  MEMDBG
1434  ( ":\nd0: %#x %#x %#x %#x\nd1: %#x %#x %#x %#x\nd2: %#x %#x %#x %#x\nd3: %#x %#x %#x %#x\n",
1435  reg.descrip[0], reg.descrip[1], reg.descrip[2], reg.descrip[3],
1436  reg.descrip[4], reg.descrip[5], reg.descrip[6], reg.descrip[7],
1437  reg.descrip[8], reg.descrip[9], reg.descrip[10], reg.descrip[11],
1438  reg.descrip[12], reg.descrip[13], reg.descrip[14], reg.descrip[15] );
1439 
1440  count = reg.descrip[0]; /* # times to repeat CPUID call. Not implemented. */
1441 
1442  /* Knights Corner at least returns 0 here */
1443  if (count==0) goto early_exit;
1444 
1445  size = ( sizeof ( intel_cache ) / sizeof ( struct _intel_cache_info ) ); /* # descriptors */
1446  MEMDBG( "Repeat cpuid(2,...) %d times. If not 1, code is broken.\n",
1447  count );
1448  if (count!=1) {
1449  fprintf(stderr,"Warning: Unhandled cpuid count of %d\n",count);
1450  }
1451 
1452  for ( r = 0; r < 4; r++ ) { /* walk the registers */
1453  if ( ( reg.descrip[r * 4 + 3] & 0x80 ) == 0 ) { /* only process if high order bit is 0 */
1454  for ( b = 3; b >= 0; b-- ) { /* walk the descriptor bytes from high to low */
1455  i = r * 4 + b; /* calculate an index into the array of descriptors */
1456  if ( i ) { /* skip the low order byte in eax [0]; it's the count (see above) */
1457  if ( reg.descrip[i] == 0xff ) {
1458  MEMDBG("Warning! PAPI x86_cache: must implement cpuid leaf 4\n");
1459  return PAPI_ENOSUPP;
1460  /* we might continue instead */
1461  /* in order to get TLB info */
1462  /* continue; */
1463  }
1464  for ( t = 0; t < size; t++ ) { /* walk the descriptor table */
1465  if ( reg.descrip[i] == intel_cache[t].descriptor ) { /* find match */
1466  if ( intel_cache[t].level > last_level )
1467  last_level = intel_cache[t].level;
1469  mh_info->level );
1470  }
1471  }
1472  }
1473  }
1474  }
1475  }
1476 early_exit:
1477  MEMDBG( "# of Levels: %d\n", last_level );
1478  *num_levels=last_level;
1479  return PAPI_OK;
1480 }
static void intel_decode_descriptor(struct _intel_cache_info *d, PAPI_mh_level_t *L)
static void print_intel_cache_table()
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
static struct _intel_cache_info intel_cache[]
#define PAPI_ENOSUPP
Definition: papi.h:271
return PAPI_OK
Definition: linux-nvml.c:497
int count
Definition: iozone.c:22422
#define DEBUG_MEMORY
Definition: papi_debug.h:34
t
Definition: iozone.c:23562
int i
Definition: fileop.c:140
char *long long size
Definition: iozone.c:12023
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:775
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
#define ISLEVEL(a)
Definition: papi_debug.h:54
static double b[MATRIX_SIZE][MATRIX_SIZE]
Definition: libmsr_basic.c:39

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static int init_intel_leaf4 ( PAPI_mh_info_t mh_info,
int num_levels 
)
static

Definition at line 1286 of file x86_cpuid_info.c.

1287 {
1288 
1289  unsigned int eax, ebx, ecx, edx;
1290  unsigned int maxidx, ecx_in;
1291  int next;
1292 
1293  int cache_type,cache_level,cache_selfinit,cache_fullyassoc;
1294  int cache_linesize,cache_partitions,cache_ways,cache_sets;
1295 
1297 
1298  *num_levels=0;
1299 
1300  cpuid2(&eax,&ebx,&ecx,&edx, 0, 0);
1301  maxidx = eax;
1302 
1303  if (maxidx<4) {
1304  MEMDBG("Warning! CPUID Index 4 not supported!\n");
1305  return PAPI_ENOSUPP;
1306  }
1307 
1308  ecx_in=0;
1309  while(1) {
1310  cpuid2(&eax,&ebx,&ecx,&edx, 4, ecx_in);
1311 
1312 
1313 
1314  /* decoded as per table 3-12 in Intel Software Developer's Manual Volume 2A */
1315 
1316  cache_type=eax&0x1f;
1317  if (cache_type==0) break;
1318 
1319  cache_level=(eax>>5)&0x3;
1320  cache_selfinit=(eax>>8)&0x1;
1321  cache_fullyassoc=(eax>>9)&0x1;
1322 
1323  cache_linesize=(ebx&0xfff)+1;
1324  cache_partitions=((ebx>>12)&0x3ff)+1;
1325  cache_ways=((ebx>>22)&0x3ff)+1;
1326 
1327  cache_sets=(ecx)+1;
1328 
1329  /* should we export this info?
1330 
1331  cache_maxshare=((eax>>14)&0xfff)+1;
1332  cache_maxpackage=((eax>>26)&0x3f)+1;
1333 
1334  cache_wb=(edx)&1;
1335  cache_inclusive=(edx>>1)&1;
1336  cache_indexing=(edx>>2)&1;
1337  */
1338 
1339  if (cache_level>*num_levels) *num_levels=cache_level;
1340 
1341  /* find next slot available to hold cache info */
1342  for ( next = 0; next < PAPI_MH_MAX_LEVELS - 1; next++ ) {
1343  if ( mh_info->level[cache_level-1].cache[next].type == PAPI_MH_TYPE_EMPTY ) break;
1344  }
1345 
1346  c=&(mh_info->level[cache_level-1].cache[next]);
1347 
1348  switch(cache_type) {
1349  case 1: MEMDBG("L%d Data Cache\n",cache_level);
1351  break;
1352  case 2: MEMDBG("L%d Instruction Cache\n",cache_level);
1354  break;
1355  case 3: MEMDBG("L%d Unified Cache\n",cache_level);
1357  break;
1358  }
1359 
1360  if (cache_selfinit) { MEMDBG("\tSelf-init\n"); }
1361  if (cache_fullyassoc) { MEMDBG("\tFully Associtative\n"); }
1362 
1363  //MEMDBG("\tMax logical processors sharing cache: %d\n",cache_maxshare);
1364  //MEMDBG("\tMax logical processors sharing package: %d\n",cache_maxpackage);
1365 
1366  MEMDBG("\tCache linesize: %d\n",cache_linesize);
1367 
1368  MEMDBG("\tCache partitions: %d\n",cache_partitions);
1369  MEMDBG("\tCache associaticity: %d\n",cache_ways);
1370 
1371  MEMDBG("\tCache sets: %d\n",cache_sets);
1372  MEMDBG("\tCache size = %dkB\n",
1373  (cache_ways*cache_partitions*cache_linesize*cache_sets)/1024);
1374 
1375  //MEMDBG("\tWBINVD/INVD acts on lower caches: %d\n",cache_wb);
1376  //MEMDBG("\tCache is not inclusive: %d\n",cache_inclusive);
1377  //MEMDBG("\tComplex cache indexing: %d\n",cache_indexing);
1378 
1379  c->line_size=cache_linesize;
1380  if (cache_fullyassoc) {
1381  c->associativity=SHRT_MAX;
1382  }
1383  else {
1384  c->associativity=cache_ways;
1385  }
1386  c->size=(cache_ways*cache_partitions*cache_linesize*cache_sets);
1387  c->num_lines=cache_ways*cache_partitions*cache_sets;
1388 
1389  ecx_in++;
1390  }
1391  return PAPI_OK;
1392 }
#define PAPI_MH_TYPE_INST
Definition: papi.h:730
#define PAPI_ENOSUPP
Definition: papi.h:271
static void cpuid2(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx, unsigned int index, unsigned int ecx_in)
return PAPI_OK
Definition: linux-nvml.c:497
double c
Definition: multiplex.c:22
#define PAPI_MH_TYPE_DATA
Definition: papi.h:731
#define PAPI_MH_MAX_LEVELS
Definition: papi.h:745
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:768
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:775
#define MEMDBG(format, args...)
Definition: papi_debug.h:70
nsize_list next
Definition: iozone.c:20053
#define PAPI_MH_TYPE_UNIFIED
Definition: papi.h:734
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:729

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static void init_mem_hierarchy ( PAPI_mh_info_t mh_info)
static

Definition at line 94 of file x86_cpuid_info.c.

95 {
96  int i, j;
97  PAPI_mh_level_t *L = mh_info->level;
98 
99  /* initialize entire memory hierarchy structure to benign values */
100  for ( i = 0; i < PAPI_MAX_MEM_HIERARCHY_LEVELS; i++ ) {
101  for ( j = 0; j < PAPI_MH_MAX_LEVELS; j++ ) {
102  L[i].tlb[j].type = PAPI_MH_TYPE_EMPTY;
103  L[i].tlb[j].num_entries = 0;
104  L[i].tlb[j].associativity = 0;
106  L[i].cache[j].size = 0;
107  L[i].cache[j].line_size = 0;
108  L[i].cache[j].num_lines = 0;
109  L[i].cache[j].associativity = 0;
110  }
111  }
112 }
int associativity
Definition: papi.h:753
#define PAPI_MH_MAX_LEVELS
Definition: papi.h:745
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:768
int i
Definition: fileop.c:140
PAPI_mh_level_t level[PAPI_MAX_MEM_HIERARCHY_LEVELS]
Definition: papi.h:775
PAPI_mh_tlb_info_t tlb[PAPI_MH_MAX_LEVELS]
Definition: papi.h:767
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:729
long j
Definition: iozone.c:19135
#define PAPI_MAX_MEM_HIERARCHY_LEVELS
Definition: papi.h:746

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static void intel_decode_descriptor ( struct _intel_cache_info d,
PAPI_mh_level_t L 
)
static

Definition at line 1210 of file x86_cpuid_info.c.

1211 {
1212  int i, next;
1213  int level = d->level - 1;
1216 
1217  if ( d->descriptor == 0x49 ) { /* special case */
1218  unsigned int r_eax, r_ebx, r_ecx, r_edx;
1219  r_eax = 0x1; /* function code 1: family & model */
1220  cpuid( &r_eax, &r_ebx, &r_ecx, &r_edx );
1221  /* override table for Family F, model 6 only */
1222  if ( ( r_eax & 0x0FFF3FF0 ) == 0xF60 )
1223  level = 3;
1224  }
1225  if ( d->type & PAPI_MH_TYPE_TLB ) {
1226  for ( next = 0; next < PAPI_MH_MAX_LEVELS - 1; next++ ) {
1227  if ( L[level].tlb[next].type == PAPI_MH_TYPE_EMPTY )
1228  break;
1229  }
1230  /* expand TLB entries for multiple possible page sizes */
1231  for ( i = 0; i < TLB_SIZES && next < PAPI_MH_MAX_LEVELS && d->size[i];
1232  i++, next++ ) {
1233 // printf("Level %d Descriptor: %#x TLB type %#x next: %d, i: %d\n", level, d->descriptor, d->type, next, i);
1234  t = &L[level].tlb[next];
1235  t->type = PAPI_MH_CACHE_TYPE( d->type );
1236  t->num_entries = d->entries;
1237  t->page_size = d->size[i] << 10; /* minimum page size in KB */
1238  t->associativity = d->associativity;
1239  /* another special case */
1240  if ( d->descriptor == 0xB1 && d->size[i] == 4096 )
1241  t->num_entries = d->entries / 2;
1242  }
1243  } else {
1244  for ( next = 0; next < PAPI_MH_MAX_LEVELS - 1; next++ ) {
1245  if ( L[level].cache[next].type == PAPI_MH_TYPE_EMPTY )
1246  break;
1247  }
1248 // printf("Level %d Descriptor: %#x Cache type %#x next: %d\n", level, d->descriptor, d->type, next);
1249  c = &L[level].cache[next];
1250  c->type = PAPI_MH_CACHE_TYPE( d->type );
1251  c->size = d->size[0] << 10; /* convert from KB to bytes */
1252  c->associativity = d->associativity;
1253  if ( d->line_size ) {
1254  c->line_size = d->line_size;
1255  c->num_lines = c->size / c->line_size;
1256  }
1257  }
1258 }
static void cpuid(unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d)
int size[TLB_SIZES]
int associativity
Definition: papi.h:753
double c
Definition: multiplex.c:22
#define PAPI_MH_TYPE_TLB
Definition: papi.h:743
t
Definition: iozone.c:23562
#define PAPI_MH_MAX_LEVELS
Definition: papi.h:745
PAPI_mh_cache_info_t cache[PAPI_MH_MAX_LEVELS]
Definition: papi.h:768
int i
Definition: fileop.c:140
#define TLB_SIZES
PAPI_mh_tlb_info_t tlb[PAPI_MH_MAX_LEVELS]
Definition: papi.h:767
nsize_list next
Definition: iozone.c:20053
#define PAPI_MH_TYPE_EMPTY
Definition: papi.h:729
#define PAPI_MH_CACHE_TYPE(a)
Definition: papi.h:735

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static void print_intel_cache_table ( )
static

Definition at line 1183 of file x86_cpuid_info.c.

1184 {
1185  int i, j, k =
1186  ( int ) ( sizeof ( intel_cache ) /
1187  sizeof ( struct _intel_cache_info ) );
1188  for ( i = 0; i < k; i++ ) {
1189  printf( "%d.\tDescriptor: %#x\n", i, intel_cache[i].descriptor );
1190  printf( "\t Level: %d\n", intel_cache[i].level );
1191  printf( "\t Type: %d\n", intel_cache[i].type );
1192  printf( "\t Size(s): " );
1193  for ( j = 0; j < TLB_SIZES; j++ )
1194  printf( "%d, ", intel_cache[i].size[j] );
1195  printf( "\n" );
1196  printf( "\t Assoc: %d\n", intel_cache[i].associativity );
1197  printf( "\t Sector: %d\n", intel_cache[i].sector );
1198  printf( "\t Line Size: %d\n", intel_cache[i].line_size );
1199  printf( "\t Entries: %d\n", intel_cache[i].entries );
1200  printf( "\n" );
1201  }
1202 }
static struct _intel_cache_info intel_cache[]
int i
Definition: fileop.c:140
char *long long size
Definition: iozone.c:12023
#define TLB_SIZES
int k
Definition: iozone.c:19136
printf("\tTry: -i 0 -i 1 \n\n")
int
Definition: iozone.c:18528
long j
Definition: iozone.c:19135

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Variable Documentation

struct _intel_cache_info intel_cache[]
static

Definition at line 372 of file x86_cpuid_info.c.