00001 /****************************/ 00002 /* THIS IS OPEN SOURCE CODE */ 00003 /****************************/ 00004 00005 /* 00006 * File: map-p6-2.c 00007 * Author: Harald Servat 00008 * redcrash@gmail.com 00009 */ 00010 00011 #include "freebsd.h" 00012 #include "papiStdEventDefs.h" 00013 #include "map.h" 00014 00015 /**************************************************************************** 00016 P6_2 SUBSTRATE 00017 P6_2 SUBSTRATE 00018 P6_2 SUBSTRATE (aka Pentium II) 00019 P6_2 SUBSTRATE 00020 P6_2 SUBSTRATE 00021 ****************************************************************************/ 00022 00023 /* 00024 NativeEvent_Value_P6_2_Processor must match P6_2_Processor_info 00025 */ 00026 00027 Native_Event_LabelDescription_t P6_2_Processor_info[] = 00028 { 00029 /* Common P6 counters */ 00030 { "p6-baclears", "Count the number of times a static branch prediction was made by the branch decoder because the BTB did not have a prediction." }, 00031 { "p6-br-bogus", "Count the number of bogus branches." }, 00032 { "p6-br-inst-decoded", "Count the number of branch instructions decoded." }, 00033 { "p6-br-inst-retired", "Count the number of branch instructions retired." }, 00034 { "p6-br-miss-pred-retired", "Count the number of mispredicted branch instructions retired." }, 00035 { "p6-br-miss-pred-taken-ret", "Count the number of taken mispredicted branches retired." }, 00036 { "p6-br-taken-retired", "Count the number of taken branches retired." }, 00037 { "p6-btb-misses", "Count the number of branches for which the BTB did not produce a prediction. "}, 00038 { "p6-bus-bnr-drv", "Count the number of bus clock cycles during which this processor is driving the BNR# pin." }, 00039 { "p6-bus-data-rcv", "Count the number of bus clock cycles during which this processor is receiving data." }, 00040 { "p6-bus-drdy-clocks", "Count the number of clocks during which DRDY# is asserted." }, 00041 { "p6-bus-hit-drv", "Count the number of bus clock cycles during which this processor is driving the HIT# pin." }, 00042 { "p6-bus-hitm-drv", "Count the number of bus clock cycles during which this processor is driving the HITM# pin." }, 00043 { "p6-bus-lock-clocks", "Count the number of clocks during with LOCK# is asserted on the external system bus." }, 00044 { "p6-bus-req-outstanding", "Count the number of bus requests outstanding in any given cycle." }, 00045 { "p6-bus-snoop-stall", "Count the number of clock cycles during which the bus is snoop stalled." }, 00046 { "p6-bus-tran-any", "Count the number of completed bus transactions of any kind." }, 00047 { "p6-bus-tran-brd", "Count the number of burst read transactions." }, 00048 { "p6-bus-tran-burst", "Count the number of completed burst transactions." }, 00049 { "p6-bus-tran-def", "Count the number of completed deferred transactions." }, 00050 { "p6-bus-tran-ifetch", "Count the number of completed instruction fetch transactions." }, 00051 { "p6-bus-tran-inval", "Count the number of completed invalidate transactions." }, 00052 { "p6-bus-tran-mem", "Count the number of completed memory transactions." }, 00053 { "p6-bus-tran-pwr", "Count the number of completed partial write transactions." }, 00054 { "p6-bus-tran-rfo", "Count the number of completed read-for-ownership transactions." }, 00055 { "p6-bus-trans-io", "Count the number of completed I/O transactions." }, 00056 { "p6-bus-trans-p", "Count the number of completed partial transactions." }, 00057 { "p6-bus-trans-wb", "Count the number of completed write-back transactions." }, 00058 { "p6-cpu-clk-unhalted", "Count the number of cycles during with the processor was not halted." }, 00059 { "p6-cycles-div-busy", "Count the number of cycles during which the divider is busy and cannot accept new divides." }, 00060 { "p6-cycles-in-pending-and-masked", "Count the number of processor cycles for which interrupts were disabled and interrupts were pending." }, 00061 { "p6-cycles-int-masked", "Count the number of processor cycles for which interrupts were disabled." }, 00062 { "p6-data-mem-refs", "Count all loads and all stores using any memory type, including internal retries." }, 00063 { "p6-dcu-lines-in", "Count the total lines allocated in the data cache unit." }, 00064 { "p6-dcu-m-lines-in", "Count the number of M state lines allocated in the data cache unit." }, 00065 { "p6-dcu-m-lines-out", "Count the number of M state lines evicted from the data cache unit." }, 00066 { "p6-dcu-miss-outstanding", "Count the weighted number of cycles while a data cache unit miss is outstanding, incremented by the number of outstanding cache misses at any time."}, 00067 { "p6-div", "Count the number of integer and floating-point divides including speculative divides." }, 00068 { "p6-flops", "Count the number of computational floating point operations retired." }, 00069 { "p6-fp-assist", "Count the number of floating point exceptions handled by microcode." }, 00070 { "p6-fp-comps-ops-exe", "Count the number of computation floating point operations executed." }, 00071 { "p6-hw-int-rx", "Count the number of hardware interrupts received." }, 00072 { "p6-ifu-fetch", "Count the number of instruction fetches, both cacheable and non-cacheable." }, 00073 { "p6-ifu-fetch-miss", "Count the number of instruction fetch misses" }, 00074 { "p6-ifu-mem-stall", "Count the number of cycles instruction fetch is stalled for any reason." }, 00075 { "p6-ild-stall", "Count the number of cycles the instruction length decoder is stalled." }, 00076 { "p6-inst-decoded", "Count the number of instructions decoded." }, 00077 { "p6-inst-retired", "Count the number of instructions retired." }, 00078 { "p6-itlb-miss", "Count the number of instruction TLB misses." }, 00079 { "p6-l2-ads", "Count the number of L2 address strobes." }, 00080 { "p6-l2-dbus-busy", "Count the number of cycles during which the L2 cache data bus was busy." }, 00081 { "p6-l2-dbus-busy-rd", "Count the number of cycles during which the L2 cache data bus was busy transferring read data from L2 to the processor." }, 00082 { "p6-l2-ifetch", "Count the number of L2 instruction fetches." }, 00083 { "p6-l2-ld", "Count the number of L2 data loads." }, 00084 { "p6-l2-lines-in", "Count the number of L2 lines allocated." }, 00085 { "p6-l2-lines-out", "Count the number of L2 lines evicted." }, 00086 { "p6-l2-m-lines-inm", "Count the number of modified lines allocated in L2 cache." }, 00087 { "p6-l2-m-lines-outm", "Count the number of L2 M-state lines evicted." }, 00088 { "p6-l2-rqsts", "Count the total number of L2 requests." }, 00089 { "p6-l2-st", "Count the number of L2 data stores." }, 00090 { "p6-ld-blocks", "Count the number of load operations delayed due to store buffer blocks." }, 00091 { "p6-misalign-mem-ref", "Count the number of misaligned data memory references (crossing a 64 bit boundary)." }, 00092 { "p6-mul", "Count the number of floating point multiplies." }, 00093 { "p6-partial-rat-stalls", "Count the number of cycles or events for partial stalls." }, 00094 { "p6-resource-stalls", "Count the number of cycles there was a resource related stall of any kind." }, 00095 { "p6-sb-drains", "Count the number of cycles the store buffer is draining." }, 00096 { "p6-segment-reg-loads", "Count the number of segment register loads." }, 00097 { "p6-uops-retired", "Count the number of micro-ops retired."}, 00098 /* Specific Pentium 2 counters */ 00099 { "p6-fp-mmx-trans", "Count the number of transitions between MMX and floating-point instructions." }, 00100 { "p6-mmx-assist", "Count the number of MMX assists executed" }, 00101 { "p6-mmx-instr-exec", "Count the number of MMX instructions executed" }, 00102 { "p6-mmx-instr-ret", "Count the number of MMX instructions retired." }, 00103 { "p6-mmx-sat-instr-exec", "Count the number of MMX saturating instructions executed" }, 00104 { "p6-mmx-uops-exec", "Count the number of MMX micro-ops executed" }, 00105 { "p6-ret-seg-renames", "Count the number of segment register rename events retired." }, 00106 { "p6-seg-rename-stalls", "Count the number of segment register renaming stalls" }, 00107 { NULL, NULL } 00108 }; 00109

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