./papi_mem_info in PAPI 3.7.0

Open discussion of PAPI.

./papi_mem_info in PAPI 3.7.0

Postby PeterS » Thu Nov 12, 2009 1:09 am

Hello,
I was wondering how PAPI figures out the size of L2 cache.

I'm running Ubuntu with 2.6.29-7 kernel on Intel Core2 Quad CPU Q6600 @ 2.40GHz. Intel website (http://ark.intel.com/Product.aspx?id=29765) states that this CPU has 8MB L2 cache but I'm only getting 4MB when I run papi_mem_info. I attached the output of papi_mem_info below.

Is there an obvious explanation to this discrepancy?

Thanks,

Peter

===========================================
output
===========================================
ps27@ws60:/site/local/papi_32-3.7.0/bin$ ./papi_mem_info
Memory Cache and TLB Hierarchy Information.
------------------------------------------------------------------------
TLB Information.
There may be multiple descriptors for each level of TLB
if multiple page sizes are supported.

L1 Data TLB:
Page Size: 4096 KB
Number of Entries: 32
Associativity: 4

L1 Instruction TLB:
Page Size: 4 KB
Number of Entries: 128
Associativity: 4

L1 Instruction TLB:
Page Size: 2048 KB
Number of Entries: 8
Associativity: 4

L1 Instruction TLB:
Page Size: 4096 KB
Number of Entries: 4
Associativity: 4

L1 Data TLB:
Page Size: 4096 KB
Number of Entries: 16
Associativity: 4

L1 Data TLB:
Page Size: 4 KB
Number of Entries: 256
Associativity: 4


Cache Information.

L1 Data Cache:
Total size: 32 KB
Line size: 64 B
Number of Lines: 512
Associativity: 8

L1 Instruction Cache:
Total size: 32 KB
Line size: 64 B
Number of Lines: 512
Associativity: 8

L2 Unified Cache:
Total size: 4096 KB
Line size: 64 B
Number of Lines: 65536
Associativity: 16
PeterS
 
Posts: 1
Joined: Thu Nov 12, 2009 12:56 am

Re: ./papi_mem_info in PAPI 3.7.0

Postby Dan Terpstra » Thu Nov 12, 2009 2:57 pm

PAPI extracts all this information from calls to the cpuid assembly instruction and decodes of the returned register values. It's possible that the tables for this decode haven't been updated to include all the information for this processor. We'll check into it.
Dan Terpstra
 
Posts: 57
Joined: Mon Aug 24, 2009 5:42 pm

Re: ./papi_mem_info in PAPI 3.7.0

Postby Dan Terpstra » Wed Dec 02, 2009 8:53 am

PeterS wrote:Is there an obvious explanation to this discrepancy?

As it turns out there is an obvious explanation. The Q6600 is actually a pair of dual core processors mounted on one substrate. This was Intel's early attempt at leapfrogging to a quad core configuration using existing technology. Each pair of cores has a 4 MB L2 cache, so this is what the cpuid instruction is seeing and what PAPI is reporting. Several sources quote this processor as having a 2X4 MB L2 cache, rather than quoting 8 MB cache. The following review http://xtreview.com/review157.htm has detailed descriptions and graphics of this processor.
So after carefully reviewing and updating PAPI's cache tables for Intel, it turns out PAPI was reporting the right values all along.
Sorry it took so long to provide this answer!
Dan Terpstra
 
Posts: 57
Joined: Mon Aug 24, 2009 5:42 pm


Return to General discussion

Who is online

Users browsing this forum: Yahoo [Bot] and 2 guests

cron