Measuring cache miss rate

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Measuring cache miss rate

Postby newpapiuser » Sat Feb 04, 2012 1:50 pm

Hello,

I am new to PAPI and am trying to use it to measure the cache miss rate (in different levels) of some part of my code.
The system I am working on is an Intel Core i7 2600, with 4 cores, and 3 levels of cache (L3 is shared)

I am looking for the correct events to use for cache miss rate measurement. I define the miss rate of level X as (number of misses in level X) / (total memory accesses). However, it seems that there is no supported event that would give me the denominator. Specifically, PAPI_LST_INS is not supported on my system (tested using PAPI_query_event()), nor any other set of events that would give me this number (for example, I can retrieve PAPI_L2_DCA and PAPI_L3_DCA but not PAPI_L1_DCA). For L1 I can only get miss counters (DCM, ICM, TCM), not hit or access counters. So I see no way to measure miss rate.

What am I doing wrong? Should I use different events? Or is PAPI not the tool for me??

Thanks a lot!
newpapiuser
 
Posts: 1
Joined: Sat Feb 04, 2012 1:39 pm

Re: Measuring cache miss rate

Postby vweaver1 » Tue Feb 07, 2012 6:07 pm

For SandyBridge chips (like you have) there are no access counters defined for the L1 cache. This is possibly a hardware limitation of your CPU.

It might just be that we missed the proper event when defining the preset events; you can look at the Intel Volume 3b documentation for the full
list of events and see if any of them suits your needs.
vweaver1
 
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Joined: Wed Feb 17, 2010 4:02 pm


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