This question may sound philosophical but, what is a L1D access to papi? I seems that an L1D access are all the hits and misses in the L1D cache.
I thought that an Access to L1D is a store or load operation triggered by the processor into the memory hierarchy. I'm just guessing, I have never read a formal definition for it.
Going further, if you read this document http://www.cise.ufl.edu/~sb3/files/pmc.pdf
page 41, they calculate the L1 Cache Hit Rate as "1 - (L1 Cache misses ) / (load + store)".
which, the access to the Cache (load + store) are the divisor.
Is there any way to relate the access (with its hits and misses) to loads and stores performed?.
Hope you can help me with my dilemma.
Fabrizio Barisione Biso.
Universidad Santiago de Chile.