Hello All,
I am working on intel xeon architecture with L1 cache .
Cache Information.
L1 Data Cache:
Total size: 32 KB
Line size: 64 B
Number of Lines: 512
Associativity: 8
I am running small program to calculate number of L1 misses.
And following is the code which accesses the data.
int *temp = (int*) malloc(1024*1024*sizeof(int));
if ((retval = PAPI_start(EventSet)) != PAPI_OK)
test_fail(__FILE__, __LINE__, "PAPI_start", retval);
for(i=0;i<8192;i++){
temp[i] = 10;
}
if ((retval = PAPI_read(EventSet,&values[0])) != PAPI_OK)
test_fail(__FILE__, __LINE__, "PAPI_read", retval);
I am expecting 512 L1 cache misses, its giving around 150 l1 misses that is also fluctuating for evry execution.
Am I missing anything? Any help would be appreciated.