L3 cache counters for Core i7

L3 cache counters for Core i7

Postby mhowison » Wed Nov 11, 2009 3:34 pm

Hello,

Is it possible to count L3 cache hits/misses on an Xeon 5550 (i7)? With PAPI 3.7 installed, papi_avail shows no support for any L3 counters. Are there plans to add support in the future? Or is it not possible to count L3 events by design of the hardware counters?

Thanks,
Mark Howison
Visualization Group
Lawrence Berkeley National Lab
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Re: L3 cache counters for Core i7

Postby jagode00 » Wed Nov 11, 2009 3:59 pm

The L3 cache on i7 is shared between all cores on the chip. When an L3 event is programmed into one counter on one core, it gets copied by hardware to a shared shadow register. Unfortunately, the results become unclear when multiple cores try to share these shadow registers. That's basically the main reason why these counters are currently not available from PAPI. If you ensure that you only use one core per chip, then you can always use the native L3 events to count L3 cache hits/misses.

-heike.
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Re: L3 cache counters for Core i7

Postby jagode00 » Wed Nov 11, 2009 5:19 pm

Hmm, actually what I just said is what's happening on the AMD Opteron processor and NOT on i7. My apologies for the confusion! :oops:
The correct answer for i7 will follow in a bit.

-heike
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Re: L3 cache counters for Core i7

Postby Dan Terpstra » Wed Nov 11, 2009 5:31 pm

Heike was correct that Core i7 has an L3 cache that is shared by all cores on the chip. However the counters that measure activity in that cache are broken in a totally different way than they are broken on AMD. Intel implemented a rich set of counters for i7: each core has 3 fixed and 4 programmable hardware counters. In addition, there are 8 counters in what Intel calls the "Uncore" on the chip, rather than on any specific core. It is these uncore counters that measure L3 activity. Unfortunately, current interfaces only allow access to these counters in global counting mode, across all processors and processes. PAPI doesn't use that mode, so these events are unavailable.
This may change at some point in the future, but will require a rewrite of the low level kernel drivers that provide access to these resources.
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