diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..1ca5b50 Binary files /dev/null and b/.gitattributes differ diff --git a/ChangeLogP501.txt b/ChangeLogP501.txt new file mode 100644 index 0000000..68ca1c7 --- /dev/null +++ b/ChangeLogP501.txt @@ -0,0 +1,77 @@ +2012-09-20 + + * 708d173a man/man1/papi_avail.1 man/man1/papi_clockres.1 + man/man1/papi_command_line.1...: Rebuild the manpages for a 5.0.1 release. + +2012-09-19 + + * 29cdd839 doc/Doxyfile-common papi.spec src/Makefile.in...: Bump the version + number for a 5.0.1 release. + + * bb7727f6 src/libpfm4/examples/fo src/libpfm4/examples/injectevt.c + .../bin/usr/local/include/perfmon/perf_event.h...: Cleanup a botched libpfm4 + update. As Steve Kaufmann noted, I botched an update of libpfm4. + +2012-09-18 + + * dc117410 src/configure src/configure.in: Remove a trailing slash in libpfm4 + pathing. Addresses an issue in rpmbuild when using bundled libpfm4. Reported + and patched by William Cohen + +2012-09-17 + + * e196b89b src/components/cuda/configure src/components/cuda/configure.in: + Minor changes to CUDA configure necessary to get it running smoothly on the + Kepler architecture. + +2012-09-11 + + * 866bd51c src/papi_internal.c src/papi_preset.c: Fix preset bug The preset + code was only initializing the first element of the preset code[] array. + Thus any event with more than one subevent was not terminated at all, and the + preset code would use random garbage as presets. This exposed another + problem; half our code assumed a 0 terminated code[] array, the rest was + looking for PAPI_NULL (-1). This standardizes on PAPI_NULL, with comments. + Hopefully this might fix PAPI bug #150. This is a serious bug and should be + included in the next stable release. + +2012-08-29 + + * b978a744 src/configure src/configure.in: configure: fix autodetect perfmon + case The fixes I made yesterday to libpfm include finding broke on perfmon2 + PAPI if you were letting the library be autodetected. This change should fix + things. Tested on an actual 2.6.30 perfmon2 system. + + * 4386e6e5 src/libpfm4/Makefile src/libpfm4/README src/libpfm4/config.mk...: + Update libpfm4 included with papi to 4.3 + +2012-08-28 + + * 729a8721 src/configure src/configure.in: configure: don't check for libpfm + if incdir specified When various --with-pfm values are passed, extra checks + are done against the libpfm library. This was being done even if only the + include path was specified, which probably shouldn't be necessary. This + broke things because a recent change I made had the libpfm include path be + always valid. + + * bc9ddffc src/configure src/configure.in: Fix compiling with separate + libpfm4 The problem was if you used any of the --with-pfm-incdir type + directives to configure, it would them assume you wanted a perfmon2 build. + This removes that assumption. I did check this with perfmon2, perfctr, and + perf_event builds so hopefully I didn't break anything. + +2012-08-27 + + * 3b737198 src/papi.c src/papi_libpfm4_events.c src/papi_preset.c...: Hack + around debugging macros. Under NO_VARARG_MACROS configs the debug printing + guys become two expression statements. This is bad for code expecting eg + SUBDBG(); to be one statement. --ie-- if ( foo ) SUBDBG("Danger Will + Robinson"); ------ In order to keep the useful file and line number + expansions with out variadic macro support, we split SUBDBG into two parts; A + call to DEBUGLABEL() and friends and then a call to a function to capture the + actual informative message. So if(foo) stmt(); becomes if (foo) + print_the_debug_label(); print_your_message(...); And your message is always + printed. See papi_debug.h for what actually happens. I'm not clever enough + to work around this any other way, so I exaustivly put { }s around every case + of the above I found. (I only searched on 'DBG' so its possible I missed + some) diff --git a/RELEASENOTES.txt b/RELEASENOTES.txt index e9d2c34..95dd5a7 100644 --- a/RELEASENOTES.txt +++ b/RELEASENOTES.txt @@ -4,6 +4,31 @@ order. For details on installing PAPI on your machine, consult the INSTALL.txt file in this directory. =============================================================================== +PAPI 5.0.1 RELEASE NOTES 20 Sep 2012 +=============================================================================== +For specific and detailed information on changes made in this release, grep +ChangeLogP500.txt for keywords of interest or go directly to the PAPI git +repo. + +GENERAL NOTES +=============================================================================== +This in a bug fix release of PAPI. Including a major bug fix in the preset +code, we recommend that all users of PAPI 5.0 upgrade; see commit 866bd51c +for a detailed discussion. + +Bug Fixes: +---------- + * Debugging macros with out variadic macro support. + * Building PAPI with an external libpfm4 installation. + * Fix a major bug in the preset code. + +Enhancements: +------------- + * CUDA configure script better supports Kepler architecture. + * rapl support for IvyBridge. + * Libpfm4 updates for SandyBridge-EP counters. + +=============================================================================== PAPI 5.0.0 RELEASE NOTES 23 Aug 2012 =============================================================================== For specific and detailed information on changes made in this release, grep diff --git a/delete_before_release.sh b/delete_before_release.sh index ed2b0c5..9f44a78 100755 Binary files a/delete_before_release.sh and b/delete_before_release.sh differ diff --git a/doc/Doxyfile-common b/doc/Doxyfile-common index 878b577..d73f608 100644 --- a/doc/Doxyfile-common +++ b/doc/Doxyfile-common @@ -31,7 +31,7 @@ PROJECT_NAME = PAPI # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = 5.0.0.0 +PROJECT_NUMBER = 5.0.1.0 # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer diff --git a/man/man1/papi_avail.1 b/man/man1/papi_avail.1 index 28aff9c..7d068c1 100644 --- a/man/man1/papi_avail.1 +++ b/man/man1/papi_avail.1 @@ -1,4 +1,4 @@ -.TH "papi_avail" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_avail" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_clockres.1 b/man/man1/papi_clockres.1 index b341112..1ad5df0 100644 --- a/man/man1/papi_clockres.1 +++ b/man/man1/papi_clockres.1 @@ -1,4 +1,4 @@ -.TH "papi_clockres" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_clockres" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_command_line.1 b/man/man1/papi_command_line.1 index d5506c3..738d666 100644 --- a/man/man1/papi_command_line.1 +++ b/man/man1/papi_command_line.1 @@ -1,4 +1,4 @@ -.TH "papi_command_line" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_command_line" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_component_avail.1 b/man/man1/papi_component_avail.1 index 1907823..53f9272 100644 --- a/man/man1/papi_component_avail.1 +++ b/man/man1/papi_component_avail.1 @@ -1,4 +1,4 @@ -.TH "papi_component_avail" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_component_avail" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_cost.1 b/man/man1/papi_cost.1 index e6bfebe..d2588e3 100644 --- a/man/man1/papi_cost.1 +++ b/man/man1/papi_cost.1 @@ -1,4 +1,4 @@ -.TH "papi_cost" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_cost" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_decode.1 b/man/man1/papi_decode.1 index c8d9edb..cf7235f 100644 --- a/man/man1/papi_decode.1 +++ b/man/man1/papi_decode.1 @@ -1,4 +1,4 @@ -.TH "papi_decode" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_decode" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_error_codes.1 b/man/man1/papi_error_codes.1 index bf1ee2e..9e6c2cb 100644 --- a/man/man1/papi_error_codes.1 +++ b/man/man1/papi_error_codes.1 @@ -1,4 +1,4 @@ -.TH "papi_error_codes" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_error_codes" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_event_chooser.1 b/man/man1/papi_event_chooser.1 index d2d6622..f31d02b 100644 --- a/man/man1/papi_event_chooser.1 +++ b/man/man1/papi_event_chooser.1 @@ -1,4 +1,4 @@ -.TH "papi_event_chooser" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_event_chooser" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_mem_info.1 b/man/man1/papi_mem_info.1 index a425160..42cf3e0 100644 --- a/man/man1/papi_mem_info.1 +++ b/man/man1/papi_mem_info.1 @@ -1,4 +1,4 @@ -.TH "papi_mem_info" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_mem_info" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_multiplex_cost.1 b/man/man1/papi_multiplex_cost.1 index 32b7c3f..726554e 100644 --- a/man/man1/papi_multiplex_cost.1 +++ b/man/man1/papi_multiplex_cost.1 @@ -1,4 +1,4 @@ -.TH "papi_multiplex_cost" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_multiplex_cost" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_native_avail.1 b/man/man1/papi_native_avail.1 index 1be30a7..d171808 100644 --- a/man/man1/papi_native_avail.1 +++ b/man/man1/papi_native_avail.1 @@ -1,4 +1,4 @@ -.TH "papi_native_avail" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_native_avail" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man1/papi_xml_event_info.1 b/man/man1/papi_xml_event_info.1 index 016a7d7..b1941a1 100644 --- a/man/man1/papi_xml_event_info.1 +++ b/man/man1/papi_xml_event_info.1 @@ -1,4 +1,4 @@ -.TH "papi_xml_event_info" 1 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "papi_xml_event_info" 1 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_accum.3 b/man/man3/PAPIF_accum.3 index a4e2428..40e1007 100644 --- a/man/man3/PAPIF_accum.3 +++ b/man/man3/PAPIF_accum.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_accum" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_accum" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_accum_counters.3 b/man/man3/PAPIF_accum_counters.3 index b703998..99325db 100644 --- a/man/man3/PAPIF_accum_counters.3 +++ b/man/man3/PAPIF_accum_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_accum_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_accum_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_add_event.3 b/man/man3/PAPIF_add_event.3 index b1c96ca..4f9b7d1 100644 --- a/man/man3/PAPIF_add_event.3 +++ b/man/man3/PAPIF_add_event.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_add_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_add_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_add_events.3 b/man/man3/PAPIF_add_events.3 index a9a37da..92a538e 100644 --- a/man/man3/PAPIF_add_events.3 +++ b/man/man3/PAPIF_add_events.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_add_events" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_add_events" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_add_named_event.3 b/man/man3/PAPIF_add_named_event.3 index dc23a66..4cf52ee 100644 --- a/man/man3/PAPIF_add_named_event.3 +++ b/man/man3/PAPIF_add_named_event.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_add_named_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_add_named_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_assign_eventset_component.3 b/man/man3/PAPIF_assign_eventset_component.3 index 5ccbcdf..987c323 100644 --- a/man/man3/PAPIF_assign_eventset_component.3 +++ b/man/man3/PAPIF_assign_eventset_component.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_assign_eventset_component" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_assign_eventset_component" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_cleanup_eventset.3 b/man/man3/PAPIF_cleanup_eventset.3 index 813c20c..827eefc 100644 --- a/man/man3/PAPIF_cleanup_eventset.3 +++ b/man/man3/PAPIF_cleanup_eventset.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_cleanup_eventset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_cleanup_eventset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_create_eventset.3 b/man/man3/PAPIF_create_eventset.3 index 44bc584..f0a9b61 100644 --- a/man/man3/PAPIF_create_eventset.3 +++ b/man/man3/PAPIF_create_eventset.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_create_eventset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_create_eventset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_destroy_eventset.3 b/man/man3/PAPIF_destroy_eventset.3 index ca95712..24520a3 100644 --- a/man/man3/PAPIF_destroy_eventset.3 +++ b/man/man3/PAPIF_destroy_eventset.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_destroy_eventset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_destroy_eventset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_enum_event.3 b/man/man3/PAPIF_enum_event.3 index 30391fb..cada36c 100644 --- a/man/man3/PAPIF_enum_event.3 +++ b/man/man3/PAPIF_enum_event.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_enum_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_enum_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_event_code_to_name.3 b/man/man3/PAPIF_event_code_to_name.3 index 183fb3f..d5f47d5 100644 --- a/man/man3/PAPIF_event_code_to_name.3 +++ b/man/man3/PAPIF_event_code_to_name.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_event_code_to_name" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_event_code_to_name" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_event_name_to_code.3 b/man/man3/PAPIF_event_name_to_code.3 index 0c9a5b8..64a0ac9 100644 --- a/man/man3/PAPIF_event_name_to_code.3 +++ b/man/man3/PAPIF_event_name_to_code.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_event_name_to_code" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_event_name_to_code" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_flips.3 b/man/man3/PAPIF_flips.3 index febf62c..807059b 100644 --- a/man/man3/PAPIF_flips.3 +++ b/man/man3/PAPIF_flips.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_flips" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_flips" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_flops.3 b/man/man3/PAPIF_flops.3 index a6a15c4..1d6830d 100644 --- a/man/man3/PAPIF_flops.3 +++ b/man/man3/PAPIF_flops.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_flops" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_flops" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_clockrate.3 b/man/man3/PAPIF_get_clockrate.3 index 8d23665..d9fee2a 100644 --- a/man/man3/PAPIF_get_clockrate.3 +++ b/man/man3/PAPIF_get_clockrate.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_clockrate" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_clockrate" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_dmem_info.3 b/man/man3/PAPIF_get_dmem_info.3 index d9a605e..92ca33b 100644 --- a/man/man3/PAPIF_get_dmem_info.3 +++ b/man/man3/PAPIF_get_dmem_info.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_dmem_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_dmem_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_domain.3 b/man/man3/PAPIF_get_domain.3 index e204d51..bc08cd5 100644 --- a/man/man3/PAPIF_get_domain.3 +++ b/man/man3/PAPIF_get_domain.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_domain" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_domain" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_event_info.3 b/man/man3/PAPIF_get_event_info.3 index f14ee81..5bbe89e 100644 --- a/man/man3/PAPIF_get_event_info.3 +++ b/man/man3/PAPIF_get_event_info.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_event_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_event_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_exe_info.3 b/man/man3/PAPIF_get_exe_info.3 index d7c4c28..d5cf9f0 100644 --- a/man/man3/PAPIF_get_exe_info.3 +++ b/man/man3/PAPIF_get_exe_info.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_exe_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_exe_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_granularity.3 b/man/man3/PAPIF_get_granularity.3 index 09df106..79fb0d8 100644 --- a/man/man3/PAPIF_get_granularity.3 +++ b/man/man3/PAPIF_get_granularity.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_granularity" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_granularity" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_hardware_info.3 b/man/man3/PAPIF_get_hardware_info.3 index 5e55b93..1113ed3 100644 --- a/man/man3/PAPIF_get_hardware_info.3 +++ b/man/man3/PAPIF_get_hardware_info.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_hardware_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_hardware_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_multiplex.3 b/man/man3/PAPIF_get_multiplex.3 index f1e6f36..2e6cc03 100644 --- a/man/man3/PAPIF_get_multiplex.3 +++ b/man/man3/PAPIF_get_multiplex.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_multiplex" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_multiplex" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_preload.3 b/man/man3/PAPIF_get_preload.3 index a949122..745b361 100644 --- a/man/man3/PAPIF_get_preload.3 +++ b/man/man3/PAPIF_get_preload.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_preload" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_preload" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_real_cyc.3 b/man/man3/PAPIF_get_real_cyc.3 index d2b9d5c..a7230a1 100644 --- a/man/man3/PAPIF_get_real_cyc.3 +++ b/man/man3/PAPIF_get_real_cyc.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_real_cyc" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_real_cyc" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_real_nsec.3 b/man/man3/PAPIF_get_real_nsec.3 index 99307f5..fb6f463 100644 --- a/man/man3/PAPIF_get_real_nsec.3 +++ b/man/man3/PAPIF_get_real_nsec.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_real_nsec" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_real_nsec" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_real_usec.3 b/man/man3/PAPIF_get_real_usec.3 index cbde3ba..6b85ad0 100644 --- a/man/man3/PAPIF_get_real_usec.3 +++ b/man/man3/PAPIF_get_real_usec.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_real_usec" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_real_usec" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_virt_cyc.3 b/man/man3/PAPIF_get_virt_cyc.3 index ebcef14..bd27a04 100644 --- a/man/man3/PAPIF_get_virt_cyc.3 +++ b/man/man3/PAPIF_get_virt_cyc.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_virt_cyc" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_virt_cyc" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_get_virt_usec.3 b/man/man3/PAPIF_get_virt_usec.3 index 97c292b..66976b4 100644 --- a/man/man3/PAPIF_get_virt_usec.3 +++ b/man/man3/PAPIF_get_virt_usec.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_get_virt_usec" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_get_virt_usec" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_ipc.3 b/man/man3/PAPIF_ipc.3 index e20a600..ed23a5e 100644 --- a/man/man3/PAPIF_ipc.3 +++ b/man/man3/PAPIF_ipc.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_ipc" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_ipc" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_is_initialized.3 b/man/man3/PAPIF_is_initialized.3 index d8bfc8d..847db8a 100644 --- a/man/man3/PAPIF_is_initialized.3 +++ b/man/man3/PAPIF_is_initialized.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_is_initialized" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_is_initialized" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_library_init.3 b/man/man3/PAPIF_library_init.3 index e6c00c2..1f43627 100644 --- a/man/man3/PAPIF_library_init.3 +++ b/man/man3/PAPIF_library_init.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_library_init" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_library_init" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_lock.3 b/man/man3/PAPIF_lock.3 index 59329da..ce9747c 100644 --- a/man/man3/PAPIF_lock.3 +++ b/man/man3/PAPIF_lock.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_lock" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_lock" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_multiplex_init.3 b/man/man3/PAPIF_multiplex_init.3 index a164e33..7c88626 100644 --- a/man/man3/PAPIF_multiplex_init.3 +++ b/man/man3/PAPIF_multiplex_init.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_multiplex_init" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_multiplex_init" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_num_cmp_hwctrs.3 b/man/man3/PAPIF_num_cmp_hwctrs.3 index 464b9d6..4b92a64 100644 --- a/man/man3/PAPIF_num_cmp_hwctrs.3 +++ b/man/man3/PAPIF_num_cmp_hwctrs.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_num_cmp_hwctrs" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_num_cmp_hwctrs" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_num_counters.3 b/man/man3/PAPIF_num_counters.3 index 0435f41..5860a61 100644 --- a/man/man3/PAPIF_num_counters.3 +++ b/man/man3/PAPIF_num_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_num_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_num_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_num_events.3 b/man/man3/PAPIF_num_events.3 index 90e38b8..2c37458 100644 --- a/man/man3/PAPIF_num_events.3 +++ b/man/man3/PAPIF_num_events.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_num_events" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_num_events" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_num_hwctrs.3 b/man/man3/PAPIF_num_hwctrs.3 index ea26c1d..9ae050b 100644 --- a/man/man3/PAPIF_num_hwctrs.3 +++ b/man/man3/PAPIF_num_hwctrs.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_num_hwctrs" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_num_hwctrs" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_perror.3 b/man/man3/PAPIF_perror.3 index 265231d..52257e5 100644 --- a/man/man3/PAPIF_perror.3 +++ b/man/man3/PAPIF_perror.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_perror" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_perror" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_query_event.3 b/man/man3/PAPIF_query_event.3 index 10538af..7f53b52 100644 --- a/man/man3/PAPIF_query_event.3 +++ b/man/man3/PAPIF_query_event.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_query_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_query_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_query_named_event.3 b/man/man3/PAPIF_query_named_event.3 index a0e54b2..cd08a86 100644 --- a/man/man3/PAPIF_query_named_event.3 +++ b/man/man3/PAPIF_query_named_event.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_query_named_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_query_named_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_read.3 b/man/man3/PAPIF_read.3 index e24c295..54bb6a4 100644 --- a/man/man3/PAPIF_read.3 +++ b/man/man3/PAPIF_read.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_read" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_read" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_read_ts.3 b/man/man3/PAPIF_read_ts.3 index d0bca0b..06482a8 100644 --- a/man/man3/PAPIF_read_ts.3 +++ b/man/man3/PAPIF_read_ts.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_read_ts" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_read_ts" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_register_thread.3 b/man/man3/PAPIF_register_thread.3 index ae9bd46..bd7ad5b 100644 --- a/man/man3/PAPIF_register_thread.3 +++ b/man/man3/PAPIF_register_thread.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_register_thread" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_register_thread" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_remove_event.3 b/man/man3/PAPIF_remove_event.3 index f688494..02d5052 100644 --- a/man/man3/PAPIF_remove_event.3 +++ b/man/man3/PAPIF_remove_event.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_remove_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_remove_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_remove_events.3 b/man/man3/PAPIF_remove_events.3 index 1a97f37..b160b43 100644 --- a/man/man3/PAPIF_remove_events.3 +++ b/man/man3/PAPIF_remove_events.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_remove_events" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_remove_events" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_remove_named_event.3 b/man/man3/PAPIF_remove_named_event.3 index 8bc75eb..9d66304 100644 --- a/man/man3/PAPIF_remove_named_event.3 +++ b/man/man3/PAPIF_remove_named_event.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_remove_named_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_remove_named_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_reset.3 b/man/man3/PAPIF_reset.3 index db09e2a..6423076 100644 --- a/man/man3/PAPIF_reset.3 +++ b/man/man3/PAPIF_reset.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_reset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_reset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_cmp_domain.3 b/man/man3/PAPIF_set_cmp_domain.3 index 95831f1..05d04a8 100644 --- a/man/man3/PAPIF_set_cmp_domain.3 +++ b/man/man3/PAPIF_set_cmp_domain.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_cmp_domain" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_cmp_domain" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_cmp_granularity.3 b/man/man3/PAPIF_set_cmp_granularity.3 index ae3ac14..fe1d2f2 100644 --- a/man/man3/PAPIF_set_cmp_granularity.3 +++ b/man/man3/PAPIF_set_cmp_granularity.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_cmp_granularity" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_cmp_granularity" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_debug.3 b/man/man3/PAPIF_set_debug.3 index 18ec8f2..8f6dc3d 100644 --- a/man/man3/PAPIF_set_debug.3 +++ b/man/man3/PAPIF_set_debug.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_debug" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_debug" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_domain.3 b/man/man3/PAPIF_set_domain.3 index 6438a96..90990ac 100644 --- a/man/man3/PAPIF_set_domain.3 +++ b/man/man3/PAPIF_set_domain.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_domain" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_domain" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_event_domain.3 b/man/man3/PAPIF_set_event_domain.3 index d195da4..0123488 100644 --- a/man/man3/PAPIF_set_event_domain.3 +++ b/man/man3/PAPIF_set_event_domain.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_event_domain" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_event_domain" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_granularity.3 b/man/man3/PAPIF_set_granularity.3 index 0c89d9f..2a43670 100644 --- a/man/man3/PAPIF_set_granularity.3 +++ b/man/man3/PAPIF_set_granularity.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_granularity" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_granularity" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_inherit.3 b/man/man3/PAPIF_set_inherit.3 index e7b97eb..097704e 100644 --- a/man/man3/PAPIF_set_inherit.3 +++ b/man/man3/PAPIF_set_inherit.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_inherit" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_inherit" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_set_multiplex.3 b/man/man3/PAPIF_set_multiplex.3 index 9ce6be1..55fdc9f 100644 --- a/man/man3/PAPIF_set_multiplex.3 +++ b/man/man3/PAPIF_set_multiplex.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_set_multiplex" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_set_multiplex" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_shutdown.3 b/man/man3/PAPIF_shutdown.3 index ee8670f..95cb2fb 100644 --- a/man/man3/PAPIF_shutdown.3 +++ b/man/man3/PAPIF_shutdown.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_shutdown" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_shutdown" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_start.3 b/man/man3/PAPIF_start.3 index cdce2d1..f8429b8 100644 --- a/man/man3/PAPIF_start.3 +++ b/man/man3/PAPIF_start.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_start" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_start" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_start_counters.3 b/man/man3/PAPIF_start_counters.3 index 2d26d9d..4ec56e7 100644 --- a/man/man3/PAPIF_start_counters.3 +++ b/man/man3/PAPIF_start_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_start_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_start_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_state.3 b/man/man3/PAPIF_state.3 index 5d93881..67055cb 100644 --- a/man/man3/PAPIF_state.3 +++ b/man/man3/PAPIF_state.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_state" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_state" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_stop.3 b/man/man3/PAPIF_stop.3 index 574f762..d111680 100644 --- a/man/man3/PAPIF_stop.3 +++ b/man/man3/PAPIF_stop.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_stop" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_stop" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_stop_counters.3 b/man/man3/PAPIF_stop_counters.3 index d13a825..cecca58 100644 --- a/man/man3/PAPIF_stop_counters.3 +++ b/man/man3/PAPIF_stop_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_stop_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_stop_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_thread_id.3 b/man/man3/PAPIF_thread_id.3 index 4d1189f..d2d3d1f 100644 --- a/man/man3/PAPIF_thread_id.3 +++ b/man/man3/PAPIF_thread_id.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_thread_id" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_thread_id" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_thread_init.3 b/man/man3/PAPIF_thread_init.3 index a3b3063..bd5b5e9 100644 --- a/man/man3/PAPIF_thread_init.3 +++ b/man/man3/PAPIF_thread_init.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_thread_init" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_thread_init" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_unlock.3 b/man/man3/PAPIF_unlock.3 index 4d7a99f..1c0165d 100644 --- a/man/man3/PAPIF_unlock.3 +++ b/man/man3/PAPIF_unlock.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_unlock" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_unlock" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_unregister_thread.3 b/man/man3/PAPIF_unregister_thread.3 index d20ae17..55d9b7c 100644 --- a/man/man3/PAPIF_unregister_thread.3 +++ b/man/man3/PAPIF_unregister_thread.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_unregister_thread" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_unregister_thread" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPIF_write.3 b/man/man3/PAPIF_write.3 index 205e408..9ffd520 100644 --- a/man/man3/PAPIF_write.3 +++ b/man/man3/PAPIF_write.3 @@ -1,4 +1,4 @@ -.TH "PAPIF_write" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPIF_write" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_accum.3 b/man/man3/PAPI_accum.3 index 4cc4abd..b3d6aae 100644 --- a/man/man3/PAPI_accum.3 +++ b/man/man3/PAPI_accum.3 @@ -1,4 +1,4 @@ -.TH "PAPI_accum" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_accum" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_accum_counters.3 b/man/man3/PAPI_accum_counters.3 index 3226a4e..418810a 100644 --- a/man/man3/PAPI_accum_counters.3 +++ b/man/man3/PAPI_accum_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPI_accum_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_accum_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_add_event.3 b/man/man3/PAPI_add_event.3 index 7148c77..0062825 100644 --- a/man/man3/PAPI_add_event.3 +++ b/man/man3/PAPI_add_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_add_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_add_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_add_events.3 b/man/man3/PAPI_add_events.3 index 6b521c6..7c0b3cb 100644 --- a/man/man3/PAPI_add_events.3 +++ b/man/man3/PAPI_add_events.3 @@ -1,4 +1,4 @@ -.TH "PAPI_add_events" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_add_events" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_add_named_event.3 b/man/man3/PAPI_add_named_event.3 index 8b03d34..c856f39 100644 --- a/man/man3/PAPI_add_named_event.3 +++ b/man/man3/PAPI_add_named_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_add_named_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_add_named_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_addr_range_option_t.3 b/man/man3/PAPI_addr_range_option_t.3 index 70292ec..1cf762f 100644 --- a/man/man3/PAPI_addr_range_option_t.3 +++ b/man/man3/PAPI_addr_range_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_addr_range_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_addr_range_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_address_map_t.3 b/man/man3/PAPI_address_map_t.3 index 3fac3ad..c68de7b 100644 --- a/man/man3/PAPI_address_map_t.3 +++ b/man/man3/PAPI_address_map_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_address_map_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_address_map_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_all_thr_spec_t.3 b/man/man3/PAPI_all_thr_spec_t.3 index 607b8d0..163d734 100644 --- a/man/man3/PAPI_all_thr_spec_t.3 +++ b/man/man3/PAPI_all_thr_spec_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_all_thr_spec_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_all_thr_spec_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_assign_eventset_component.3 b/man/man3/PAPI_assign_eventset_component.3 index 0ed6604..b703309 100644 --- a/man/man3/PAPI_assign_eventset_component.3 +++ b/man/man3/PAPI_assign_eventset_component.3 @@ -1,4 +1,4 @@ -.TH "PAPI_assign_eventset_component" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_assign_eventset_component" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_attach.3 b/man/man3/PAPI_attach.3 index 431b2bb..8886ebb 100644 --- a/man/man3/PAPI_attach.3 +++ b/man/man3/PAPI_attach.3 @@ -1,4 +1,4 @@ -.TH "PAPI_attach" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_attach" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_attach_option_t.3 b/man/man3/PAPI_attach_option_t.3 index 4b54397..282e79d 100644 --- a/man/man3/PAPI_attach_option_t.3 +++ b/man/man3/PAPI_attach_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_attach_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_attach_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_cleanup_eventset.3 b/man/man3/PAPI_cleanup_eventset.3 index 572edd1..f5e866c 100644 --- a/man/man3/PAPI_cleanup_eventset.3 +++ b/man/man3/PAPI_cleanup_eventset.3 @@ -1,4 +1,4 @@ -.TH "PAPI_cleanup_eventset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_cleanup_eventset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_component_info_t.3 b/man/man3/PAPI_component_info_t.3 index 4ef4371..ffe3aad 100644 --- a/man/man3/PAPI_component_info_t.3 +++ b/man/man3/PAPI_component_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_component_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_component_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_cpu_option_t.3 b/man/man3/PAPI_cpu_option_t.3 index 7325fe2..61cb5d4 100644 --- a/man/man3/PAPI_cpu_option_t.3 +++ b/man/man3/PAPI_cpu_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_cpu_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_cpu_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_create_eventset.3 b/man/man3/PAPI_create_eventset.3 index 1eec67f..76c84fb 100644 --- a/man/man3/PAPI_create_eventset.3 +++ b/man/man3/PAPI_create_eventset.3 @@ -1,4 +1,4 @@ -.TH "PAPI_create_eventset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_create_eventset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_debug_option_t.3 b/man/man3/PAPI_debug_option_t.3 index 050e201..7bdec44 100644 --- a/man/man3/PAPI_debug_option_t.3 +++ b/man/man3/PAPI_debug_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_debug_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_debug_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_destroy_eventset.3 b/man/man3/PAPI_destroy_eventset.3 index e14a809..5e08d57 100644 --- a/man/man3/PAPI_destroy_eventset.3 +++ b/man/man3/PAPI_destroy_eventset.3 @@ -1,4 +1,4 @@ -.TH "PAPI_destroy_eventset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_destroy_eventset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_detach.3 b/man/man3/PAPI_detach.3 index 20d4fdb..7c137ad 100644 --- a/man/man3/PAPI_detach.3 +++ b/man/man3/PAPI_detach.3 @@ -1,4 +1,4 @@ -.TH "PAPI_detach" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_detach" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_disable_component.3 b/man/man3/PAPI_disable_component.3 index 8c35db2..df6cc7b 100644 --- a/man/man3/PAPI_disable_component.3 +++ b/man/man3/PAPI_disable_component.3 @@ -1,4 +1,4 @@ -.TH "PAPI_disable_component" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_disable_component" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_disable_component_by_name.3 b/man/man3/PAPI_disable_component_by_name.3 index e793cbd..70c0be8 100644 --- a/man/man3/PAPI_disable_component_by_name.3 +++ b/man/man3/PAPI_disable_component_by_name.3 @@ -1,4 +1,4 @@ -.TH "PAPI_disable_component_by_name" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_disable_component_by_name" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_dmem_info_t.3 b/man/man3/PAPI_dmem_info_t.3 index a16858a..8e57365 100644 --- a/man/man3/PAPI_dmem_info_t.3 +++ b/man/man3/PAPI_dmem_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_dmem_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_dmem_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_domain_option_t.3 b/man/man3/PAPI_domain_option_t.3 index d81e28c..d5bdbc5 100644 --- a/man/man3/PAPI_domain_option_t.3 +++ b/man/man3/PAPI_domain_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_domain_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_domain_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_enum_cmp_event.3 b/man/man3/PAPI_enum_cmp_event.3 index ce9b52c..7bb333c 100644 --- a/man/man3/PAPI_enum_cmp_event.3 +++ b/man/man3/PAPI_enum_cmp_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_enum_cmp_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_enum_cmp_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_enum_event.3 b/man/man3/PAPI_enum_event.3 index 1ca60be..46d511f 100644 --- a/man/man3/PAPI_enum_event.3 +++ b/man/man3/PAPI_enum_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_enum_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_enum_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_event_code_to_name.3 b/man/man3/PAPI_event_code_to_name.3 index 95263b2..20f1edd 100644 --- a/man/man3/PAPI_event_code_to_name.3 +++ b/man/man3/PAPI_event_code_to_name.3 @@ -1,4 +1,4 @@ -.TH "PAPI_event_code_to_name" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_event_code_to_name" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_event_info_t.3 b/man/man3/PAPI_event_info_t.3 index 0731191..7956b91 100644 --- a/man/man3/PAPI_event_info_t.3 +++ b/man/man3/PAPI_event_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_event_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_event_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_event_name_to_code.3 b/man/man3/PAPI_event_name_to_code.3 index f26dd9e..41193ff 100644 --- a/man/man3/PAPI_event_name_to_code.3 +++ b/man/man3/PAPI_event_name_to_code.3 @@ -1,4 +1,4 @@ -.TH "PAPI_event_name_to_code" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_event_name_to_code" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_exe_info_t.3 b/man/man3/PAPI_exe_info_t.3 index 0d9a5be..6539b48 100644 --- a/man/man3/PAPI_exe_info_t.3 +++ b/man/man3/PAPI_exe_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_exe_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_exe_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_flips.3 b/man/man3/PAPI_flips.3 index 5d3a275..638025c 100644 --- a/man/man3/PAPI_flips.3 +++ b/man/man3/PAPI_flips.3 @@ -1,4 +1,4 @@ -.TH "PAPI_flips" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_flips" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_flops.3 b/man/man3/PAPI_flops.3 index 5bd92ab..61f58da 100644 --- a/man/man3/PAPI_flops.3 +++ b/man/man3/PAPI_flops.3 @@ -1,4 +1,4 @@ -.TH "PAPI_flops" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_flops" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_cmp_opt.3 b/man/man3/PAPI_get_cmp_opt.3 index 6af6e3a..a189807 100644 --- a/man/man3/PAPI_get_cmp_opt.3 +++ b/man/man3/PAPI_get_cmp_opt.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_cmp_opt" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_cmp_opt" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_component_index.3 b/man/man3/PAPI_get_component_index.3 index f43f219..3dafed5 100644 --- a/man/man3/PAPI_get_component_index.3 +++ b/man/man3/PAPI_get_component_index.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_component_index" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_component_index" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_component_info.3 b/man/man3/PAPI_get_component_info.3 index b75864f..be33a65 100644 --- a/man/man3/PAPI_get_component_info.3 +++ b/man/man3/PAPI_get_component_info.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_component_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_component_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_dmem_info.3 b/man/man3/PAPI_get_dmem_info.3 index 0ff8158..d82ec80 100644 --- a/man/man3/PAPI_get_dmem_info.3 +++ b/man/man3/PAPI_get_dmem_info.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_dmem_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_dmem_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_event_component.3 b/man/man3/PAPI_get_event_component.3 index 34e5c2d..983c912 100644 --- a/man/man3/PAPI_get_event_component.3 +++ b/man/man3/PAPI_get_event_component.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_event_component" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_event_component" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_event_info.3 b/man/man3/PAPI_get_event_info.3 index b6b76ab..84170d9 100644 --- a/man/man3/PAPI_get_event_info.3 +++ b/man/man3/PAPI_get_event_info.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_event_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_event_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_executable_info.3 b/man/man3/PAPI_get_executable_info.3 index 5cfff50..de9aff5 100644 --- a/man/man3/PAPI_get_executable_info.3 +++ b/man/man3/PAPI_get_executable_info.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_executable_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_executable_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_hardware_info.3 b/man/man3/PAPI_get_hardware_info.3 index d1c5964..7b49f7c 100644 --- a/man/man3/PAPI_get_hardware_info.3 +++ b/man/man3/PAPI_get_hardware_info.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_hardware_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_hardware_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_multiplex.3 b/man/man3/PAPI_get_multiplex.3 index 1007091..274f6d3 100644 --- a/man/man3/PAPI_get_multiplex.3 +++ b/man/man3/PAPI_get_multiplex.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_multiplex" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_multiplex" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_opt.3 b/man/man3/PAPI_get_opt.3 index defdd49..9c0f997 100644 --- a/man/man3/PAPI_get_opt.3 +++ b/man/man3/PAPI_get_opt.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_opt" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_opt" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_overflow_event_index.3 b/man/man3/PAPI_get_overflow_event_index.3 index 099ab49..83ec6db 100644 --- a/man/man3/PAPI_get_overflow_event_index.3 +++ b/man/man3/PAPI_get_overflow_event_index.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_overflow_event_index" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_overflow_event_index" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_real_cyc.3 b/man/man3/PAPI_get_real_cyc.3 index b5c7338..9e2bb1d 100644 --- a/man/man3/PAPI_get_real_cyc.3 +++ b/man/man3/PAPI_get_real_cyc.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_real_cyc" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_real_cyc" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_real_nsec.3 b/man/man3/PAPI_get_real_nsec.3 index 75f55fc..5c0a54e 100644 --- a/man/man3/PAPI_get_real_nsec.3 +++ b/man/man3/PAPI_get_real_nsec.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_real_nsec" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_real_nsec" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_real_usec.3 b/man/man3/PAPI_get_real_usec.3 index 2527eb1..984ad59 100644 --- a/man/man3/PAPI_get_real_usec.3 +++ b/man/man3/PAPI_get_real_usec.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_real_usec" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_real_usec" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_shared_lib_info.3 b/man/man3/PAPI_get_shared_lib_info.3 index dfcb098..a60adfe 100644 --- a/man/man3/PAPI_get_shared_lib_info.3 +++ b/man/man3/PAPI_get_shared_lib_info.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_shared_lib_info" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_shared_lib_info" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_thr_specific.3 b/man/man3/PAPI_get_thr_specific.3 index 440b9cd..ad4815d 100644 --- a/man/man3/PAPI_get_thr_specific.3 +++ b/man/man3/PAPI_get_thr_specific.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_thr_specific" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_thr_specific" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_virt_cyc.3 b/man/man3/PAPI_get_virt_cyc.3 index a48b26b..a1ef4b2 100644 --- a/man/man3/PAPI_get_virt_cyc.3 +++ b/man/man3/PAPI_get_virt_cyc.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_virt_cyc" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_virt_cyc" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_virt_nsec.3 b/man/man3/PAPI_get_virt_nsec.3 index 7e7449c..ca39c34 100644 --- a/man/man3/PAPI_get_virt_nsec.3 +++ b/man/man3/PAPI_get_virt_nsec.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_virt_nsec" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_virt_nsec" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_get_virt_usec.3 b/man/man3/PAPI_get_virt_usec.3 index 09c554d..cb2cc52 100644 --- a/man/man3/PAPI_get_virt_usec.3 +++ b/man/man3/PAPI_get_virt_usec.3 @@ -1,4 +1,4 @@ -.TH "PAPI_get_virt_usec" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_get_virt_usec" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_granularity_option_t.3 b/man/man3/PAPI_granularity_option_t.3 index 60908d7..45bb3da 100644 --- a/man/man3/PAPI_granularity_option_t.3 +++ b/man/man3/PAPI_granularity_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_granularity_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_granularity_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_hw_info_t.3 b/man/man3/PAPI_hw_info_t.3 index 3ae6e74..fe55bd6 100644 --- a/man/man3/PAPI_hw_info_t.3 +++ b/man/man3/PAPI_hw_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_hw_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_hw_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_inherit_option_t.3 b/man/man3/PAPI_inherit_option_t.3 index 3392d90..4e0906a 100644 --- a/man/man3/PAPI_inherit_option_t.3 +++ b/man/man3/PAPI_inherit_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_inherit_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_inherit_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_ipc.3 b/man/man3/PAPI_ipc.3 index ca2f6a2..67f11eb 100644 --- a/man/man3/PAPI_ipc.3 +++ b/man/man3/PAPI_ipc.3 @@ -1,4 +1,4 @@ -.TH "PAPI_ipc" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_ipc" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_is_initialized.3 b/man/man3/PAPI_is_initialized.3 index 4456c61..18d98fc 100644 --- a/man/man3/PAPI_is_initialized.3 +++ b/man/man3/PAPI_is_initialized.3 @@ -1,4 +1,4 @@ -.TH "PAPI_is_initialized" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_is_initialized" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_itimer_option_t.3 b/man/man3/PAPI_itimer_option_t.3 index 276baaa..746a19b 100644 --- a/man/man3/PAPI_itimer_option_t.3 +++ b/man/man3/PAPI_itimer_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_itimer_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_itimer_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_library_init.3 b/man/man3/PAPI_library_init.3 index e82389f..a145995 100644 --- a/man/man3/PAPI_library_init.3 +++ b/man/man3/PAPI_library_init.3 @@ -1,4 +1,4 @@ -.TH "PAPI_library_init" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_library_init" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_list_events.3 b/man/man3/PAPI_list_events.3 index e0bde82..eb0414d 100644 --- a/man/man3/PAPI_list_events.3 +++ b/man/man3/PAPI_list_events.3 @@ -1,4 +1,4 @@ -.TH "PAPI_list_events" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_list_events" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_list_threads.3 b/man/man3/PAPI_list_threads.3 index 1793c33..def8b83 100644 --- a/man/man3/PAPI_list_threads.3 +++ b/man/man3/PAPI_list_threads.3 @@ -1,4 +1,4 @@ -.TH "PAPI_list_threads" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_list_threads" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_lock.3 b/man/man3/PAPI_lock.3 index 0de0208..2885078 100644 --- a/man/man3/PAPI_lock.3 +++ b/man/man3/PAPI_lock.3 @@ -1,4 +1,4 @@ -.TH "PAPI_lock" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_lock" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_mh_cache_info_t.3 b/man/man3/PAPI_mh_cache_info_t.3 index 28c5bdc..e0ef9b8 100644 --- a/man/man3/PAPI_mh_cache_info_t.3 +++ b/man/man3/PAPI_mh_cache_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_mh_cache_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_mh_cache_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_mh_info_t.3 b/man/man3/PAPI_mh_info_t.3 index ce7f8f9..e64325c 100644 --- a/man/man3/PAPI_mh_info_t.3 +++ b/man/man3/PAPI_mh_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_mh_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_mh_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_mh_level_t.3 b/man/man3/PAPI_mh_level_t.3 index f13b2a1..b8007be 100644 --- a/man/man3/PAPI_mh_level_t.3 +++ b/man/man3/PAPI_mh_level_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_mh_level_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_mh_level_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_mh_tlb_info_t.3 b/man/man3/PAPI_mh_tlb_info_t.3 index 2e7fb5f..cbe7136 100644 --- a/man/man3/PAPI_mh_tlb_info_t.3 +++ b/man/man3/PAPI_mh_tlb_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_mh_tlb_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_mh_tlb_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_mpx_info_t.3 b/man/man3/PAPI_mpx_info_t.3 index 0437d39..19666a9 100644 --- a/man/man3/PAPI_mpx_info_t.3 +++ b/man/man3/PAPI_mpx_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_mpx_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_mpx_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_multiplex_init.3 b/man/man3/PAPI_multiplex_init.3 index 4adc443..a13015a 100644 --- a/man/man3/PAPI_multiplex_init.3 +++ b/man/man3/PAPI_multiplex_init.3 @@ -1,4 +1,4 @@ -.TH "PAPI_multiplex_init" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_multiplex_init" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_multiplex_option_t.3 b/man/man3/PAPI_multiplex_option_t.3 index f0ad772..276ae01 100644 --- a/man/man3/PAPI_multiplex_option_t.3 +++ b/man/man3/PAPI_multiplex_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_multiplex_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_multiplex_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_num_cmp_hwctrs.3 b/man/man3/PAPI_num_cmp_hwctrs.3 index afba647..c9c2893 100644 --- a/man/man3/PAPI_num_cmp_hwctrs.3 +++ b/man/man3/PAPI_num_cmp_hwctrs.3 @@ -1,4 +1,4 @@ -.TH "PAPI_num_cmp_hwctrs" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_num_cmp_hwctrs" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_num_components.3 b/man/man3/PAPI_num_components.3 index 0307bd7..4d6ee86 100644 --- a/man/man3/PAPI_num_components.3 +++ b/man/man3/PAPI_num_components.3 @@ -1,4 +1,4 @@ -.TH "PAPI_num_components" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_num_components" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_num_counters.3 b/man/man3/PAPI_num_counters.3 index 177e63d..55195e2 100644 --- a/man/man3/PAPI_num_counters.3 +++ b/man/man3/PAPI_num_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPI_num_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_num_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_num_events.3 b/man/man3/PAPI_num_events.3 index 3742182..008e2c7 100644 --- a/man/man3/PAPI_num_events.3 +++ b/man/man3/PAPI_num_events.3 @@ -1,4 +1,4 @@ -.TH "PAPI_num_events" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_num_events" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_num_hwctrs.3 b/man/man3/PAPI_num_hwctrs.3 index 87d0b50..b590cf2 100644 --- a/man/man3/PAPI_num_hwctrs.3 +++ b/man/man3/PAPI_num_hwctrs.3 @@ -1,4 +1,4 @@ -.TH "PAPI_num_hwctrs" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_num_hwctrs" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_option_t.3 b/man/man3/PAPI_option_t.3 index 387167c..08d8645 100644 --- a/man/man3/PAPI_option_t.3 +++ b/man/man3/PAPI_option_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_option_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_option_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_overflow.3 b/man/man3/PAPI_overflow.3 index 9912ad7..affd0e1 100644 --- a/man/man3/PAPI_overflow.3 +++ b/man/man3/PAPI_overflow.3 @@ -1,4 +1,4 @@ -.TH "PAPI_overflow" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_overflow" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_perror.3 b/man/man3/PAPI_perror.3 index 5a217ec..e9519dc 100644 --- a/man/man3/PAPI_perror.3 +++ b/man/man3/PAPI_perror.3 @@ -1,4 +1,4 @@ -.TH "PAPI_perror" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_perror" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_preload_info_t.3 b/man/man3/PAPI_preload_info_t.3 index c064b0d..8117170 100644 --- a/man/man3/PAPI_preload_info_t.3 +++ b/man/man3/PAPI_preload_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_preload_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_preload_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_profil.3 b/man/man3/PAPI_profil.3 index 8bfa6cc..98c41b0 100644 --- a/man/man3/PAPI_profil.3 +++ b/man/man3/PAPI_profil.3 @@ -1,4 +1,4 @@ -.TH "PAPI_profil" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_profil" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_query_event.3 b/man/man3/PAPI_query_event.3 index d31db61..eedcdbb 100644 --- a/man/man3/PAPI_query_event.3 +++ b/man/man3/PAPI_query_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_query_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_query_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_query_named_event.3 b/man/man3/PAPI_query_named_event.3 index ecc59af..c6039b2 100644 --- a/man/man3/PAPI_query_named_event.3 +++ b/man/man3/PAPI_query_named_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_query_named_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_query_named_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_read.3 b/man/man3/PAPI_read.3 index d9f4154..de7e90f 100644 --- a/man/man3/PAPI_read.3 +++ b/man/man3/PAPI_read.3 @@ -1,4 +1,4 @@ -.TH "PAPI_read" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_read" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_read_counters.3 b/man/man3/PAPI_read_counters.3 index 2ca9988..eb8ac92 100644 --- a/man/man3/PAPI_read_counters.3 +++ b/man/man3/PAPI_read_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPI_read_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_read_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_read_ts.3 b/man/man3/PAPI_read_ts.3 index 5a7ee67..dac8529 100644 --- a/man/man3/PAPI_read_ts.3 +++ b/man/man3/PAPI_read_ts.3 @@ -1,4 +1,4 @@ -.TH "PAPI_read_ts" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_read_ts" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_register_thread.3 b/man/man3/PAPI_register_thread.3 index 3e85e65..c36d07d 100644 --- a/man/man3/PAPI_register_thread.3 +++ b/man/man3/PAPI_register_thread.3 @@ -1,4 +1,4 @@ -.TH "PAPI_register_thread" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_register_thread" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_remove_event.3 b/man/man3/PAPI_remove_event.3 index d468126..ad0f78f 100644 --- a/man/man3/PAPI_remove_event.3 +++ b/man/man3/PAPI_remove_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_remove_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_remove_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_remove_events.3 b/man/man3/PAPI_remove_events.3 index 6ee497d..b87486e 100644 --- a/man/man3/PAPI_remove_events.3 +++ b/man/man3/PAPI_remove_events.3 @@ -1,4 +1,4 @@ -.TH "PAPI_remove_events" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_remove_events" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_remove_named_event.3 b/man/man3/PAPI_remove_named_event.3 index a60391e..b985e97 100644 --- a/man/man3/PAPI_remove_named_event.3 +++ b/man/man3/PAPI_remove_named_event.3 @@ -1,4 +1,4 @@ -.TH "PAPI_remove_named_event" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_remove_named_event" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_reset.3 b/man/man3/PAPI_reset.3 index dddbe85..9326bea 100644 --- a/man/man3/PAPI_reset.3 +++ b/man/man3/PAPI_reset.3 @@ -1,4 +1,4 @@ -.TH "PAPI_reset" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_reset" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_cmp_domain.3 b/man/man3/PAPI_set_cmp_domain.3 index a0d14b8..92a5242 100644 --- a/man/man3/PAPI_set_cmp_domain.3 +++ b/man/man3/PAPI_set_cmp_domain.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_cmp_domain" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_cmp_domain" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_cmp_granularity.3 b/man/man3/PAPI_set_cmp_granularity.3 index 0b75041..34ff09d 100644 --- a/man/man3/PAPI_set_cmp_granularity.3 +++ b/man/man3/PAPI_set_cmp_granularity.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_cmp_granularity" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_cmp_granularity" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_debug.3 b/man/man3/PAPI_set_debug.3 index 52459c1..0d7db78 100644 --- a/man/man3/PAPI_set_debug.3 +++ b/man/man3/PAPI_set_debug.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_debug" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_debug" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_domain.3 b/man/man3/PAPI_set_domain.3 index db7602e..2e992c8 100644 --- a/man/man3/PAPI_set_domain.3 +++ b/man/man3/PAPI_set_domain.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_domain" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_domain" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_granularity.3 b/man/man3/PAPI_set_granularity.3 index 9938f25..ff2fb4c 100644 --- a/man/man3/PAPI_set_granularity.3 +++ b/man/man3/PAPI_set_granularity.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_granularity" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_granularity" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_multiplex.3 b/man/man3/PAPI_set_multiplex.3 index db7dea2..d704a40 100644 --- a/man/man3/PAPI_set_multiplex.3 +++ b/man/man3/PAPI_set_multiplex.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_multiplex" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_multiplex" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_opt.3 b/man/man3/PAPI_set_opt.3 index 04e387b..115d18a 100644 --- a/man/man3/PAPI_set_opt.3 +++ b/man/man3/PAPI_set_opt.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_opt" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_opt" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_set_thr_specific.3 b/man/man3/PAPI_set_thr_specific.3 index ccc254a..d278f09 100644 --- a/man/man3/PAPI_set_thr_specific.3 +++ b/man/man3/PAPI_set_thr_specific.3 @@ -1,4 +1,4 @@ -.TH "PAPI_set_thr_specific" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_set_thr_specific" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_shlib_info_t.3 b/man/man3/PAPI_shlib_info_t.3 index b8e59de..7a6279e 100644 --- a/man/man3/PAPI_shlib_info_t.3 +++ b/man/man3/PAPI_shlib_info_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_shlib_info_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_shlib_info_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_shutdown.3 b/man/man3/PAPI_shutdown.3 index fd162dd..e56c9ba 100644 --- a/man/man3/PAPI_shutdown.3 +++ b/man/man3/PAPI_shutdown.3 @@ -1,4 +1,4 @@ -.TH "PAPI_shutdown" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_shutdown" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_sprofil.3 b/man/man3/PAPI_sprofil.3 index 3629476..a3dfcfa 100644 --- a/man/man3/PAPI_sprofil.3 +++ b/man/man3/PAPI_sprofil.3 @@ -1,4 +1,4 @@ -.TH "PAPI_sprofil" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_sprofil" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_sprofil_t.3 b/man/man3/PAPI_sprofil_t.3 index 93e6357..43680f6 100644 --- a/man/man3/PAPI_sprofil_t.3 +++ b/man/man3/PAPI_sprofil_t.3 @@ -1,4 +1,4 @@ -.TH "PAPI_sprofil_t" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_sprofil_t" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_start.3 b/man/man3/PAPI_start.3 index 6047151..5cd8453 100644 --- a/man/man3/PAPI_start.3 +++ b/man/man3/PAPI_start.3 @@ -1,4 +1,4 @@ -.TH "PAPI_start" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_start" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_start_counters.3 b/man/man3/PAPI_start_counters.3 index 8c97ae5..84b73cc 100644 --- a/man/man3/PAPI_start_counters.3 +++ b/man/man3/PAPI_start_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPI_start_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_start_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_state.3 b/man/man3/PAPI_state.3 index 682d999..acb8f1e 100644 --- a/man/man3/PAPI_state.3 +++ b/man/man3/PAPI_state.3 @@ -1,4 +1,4 @@ -.TH "PAPI_state" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_state" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_stop.3 b/man/man3/PAPI_stop.3 index 9d756b3..95905e7 100644 --- a/man/man3/PAPI_stop.3 +++ b/man/man3/PAPI_stop.3 @@ -1,4 +1,4 @@ -.TH "PAPI_stop" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_stop" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_stop_counters.3 b/man/man3/PAPI_stop_counters.3 index a0bdf7c..c8a1e59 100644 --- a/man/man3/PAPI_stop_counters.3 +++ b/man/man3/PAPI_stop_counters.3 @@ -1,4 +1,4 @@ -.TH "PAPI_stop_counters" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_stop_counters" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_strerror.3 b/man/man3/PAPI_strerror.3 index 8deeedf..2a2204b 100644 --- a/man/man3/PAPI_strerror.3 +++ b/man/man3/PAPI_strerror.3 @@ -1,4 +1,4 @@ -.TH "PAPI_strerror" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_strerror" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_thread_id.3 b/man/man3/PAPI_thread_id.3 index 59904be..e7d6819 100644 --- a/man/man3/PAPI_thread_id.3 +++ b/man/man3/PAPI_thread_id.3 @@ -1,4 +1,4 @@ -.TH "PAPI_thread_id" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_thread_id" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_thread_init.3 b/man/man3/PAPI_thread_init.3 index f864cbc..5bb8799 100644 --- a/man/man3/PAPI_thread_init.3 +++ b/man/man3/PAPI_thread_init.3 @@ -1,4 +1,4 @@ -.TH "PAPI_thread_init" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_thread_init" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_unlock.3 b/man/man3/PAPI_unlock.3 index 208bf48..c6ecee7 100644 --- a/man/man3/PAPI_unlock.3 +++ b/man/man3/PAPI_unlock.3 @@ -1,4 +1,4 @@ -.TH "PAPI_unlock" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_unlock" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_unregister_thread.3 b/man/man3/PAPI_unregister_thread.3 index 31fc1d0..6b51877 100644 --- a/man/man3/PAPI_unregister_thread.3 +++ b/man/man3/PAPI_unregister_thread.3 @@ -1,4 +1,4 @@ -.TH "PAPI_unregister_thread" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_unregister_thread" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/man/man3/PAPI_write.3 b/man/man3/PAPI_write.3 index 9253731..213c7cd 100644 --- a/man/man3/PAPI_write.3 +++ b/man/man3/PAPI_write.3 @@ -1,4 +1,4 @@ -.TH "PAPI_write" 3 "Thu Aug 23 2012" "Version 5.0.0.0" "PAPI" \" -*- nroff -*- +.TH "PAPI_write" 3 "Thu Sep 20 2012" "Version 5.0.1.0" "PAPI" \" -*- nroff -*- .ad l .nh .SH NAME diff --git a/papi.spec b/papi.spec index 139595e..b25858b 100644 --- a/papi.spec +++ b/papi.spec @@ -1,6 +1,6 @@ Summary: Performance Application Programming Interface Name: papi -Version: 5.0.0.0 +Version: 5.0.1.0 Release: 1%{?dist} License: BSD Group: Development/System diff --git a/release_procedure.txt b/release_procedure.txt index ef02afa..8ed2c25 100644 Binary files a/release_procedure.txt and b/release_procedure.txt differ diff --git a/src/Makefile.in b/src/Makefile.in index 66bea1f..9b73510 100644 --- a/src/Makefile.in +++ b/src/Makefile.in @@ -1,6 +1,6 @@ PAPIVER=5 PAPIREV=0 -PAPIAGE=0 +PAPIAGE=1 PAPIINC=0 PREFIX = @prefix@ prefix = $(PREFIX) diff --git a/src/Rules.pfm4_pe b/src/Rules.pfm4_pe index 25e7441..56a2f07 100644 --- a/src/Rules.pfm4_pe +++ b/src/Rules.pfm4_pe @@ -2,23 +2,23 @@ DESCR = "Linux with perf_event kernel support and libpfm4" ifneq (/usr,$(PFM_PREFIX)) -PWD = $(shell pwd) -ifeq (,$(PFM_LIB_PATH)) -ifeq (,$(PFM_ROOT)) - PFM_ROOT := $(PWD)/libpfm4 -endif - PFM_LIB_PATH := $(PFM_ROOT)/lib - CC_SHR += -Wl,-rpath-link -Wl,$(PFM_LIB_PATH) -endif -ifeq (,$(PFM_INC_PATH)) -ifeq (,$(PFM_ROOT)) - PFM_ROOT := $(PWD)/libpfm4 -endif - PFM_INC_PATH := $(PFM_ROOT)/include -endif -ifneq (/usr/include,$(PFM_INC_PATH)) -CFLAGS += -I$(PFM_INC_PATH) -endif + PWD = $(shell pwd) + ifeq (,$(PFM_LIB_PATH)) + ifeq (,$(PFM_ROOT)) + PFM_ROOT := $(PWD)/libpfm4 + endif + PFM_LIB_PATH := $(PFM_ROOT)/lib + CC_SHR += -Wl,-rpath-link -Wl,$(PFM_LIB_PATH) + endif + ifeq (,$(PFM_INC_PATH)) + ifeq (,$(PFM_ROOT)) + PFM_ROOT := $(PWD)/libpfm4 + endif + PFM_INC_PATH := $(PFM_ROOT)/include + endif + ifneq (/usr/include,$(PFM_INC_PATH)) + CFLAGS += -I$(PFM_INC_PATH) + endif endif MISCHDRS += linux-lock.h mb.h papi_libpfm4_events.h $(PAPI_EVENTS_TABLE) diff --git a/src/components/cuda/configure b/src/components/cuda/configure index 732d4e8..1da96b6 100755 --- a/src/components/cuda/configure +++ b/src/components/cuda/configure @@ -2300,15 +2300,16 @@ nvcc_version=`nvcc -V 2>&1 | tail -n 1 | awk '{printf $5}'` major=`echo $nvcc_version | sed 's/\([^.][^.]*\).*/\1/'` minor=`echo $nvcc_version | sed 's/[^.][^.]*.\([^.,][^.,]*\).*/\1/'` +echo "CUDA $major.$minor used" + +if test "$major" -lt 4; then + echo "CUDA $major.$minor not supported" +fi + if test "$major" -eq 4; then - if test "$minor" -ge 1; then - echo "CUDA $major.$minor used" - else - echo "CUDA $major.$minor used" + if test "$minor" -eq 0; then CUDA_VERSION="-DCUDA_4_0" fi -else - echo "CUDA $major.$minor not supported" fi ac_config_files="$ac_config_files Makefile.cuda" diff --git a/src/components/cuda/configure.in b/src/components/cuda/configure.in index 6048a88..fd8a275 100644 --- a/src/components/cuda/configure.in +++ b/src/components/cuda/configure.in @@ -33,15 +33,16 @@ nvcc_version=`nvcc -V 2>&1 | tail -n 1 | awk '{printf $5}'` major=`echo $nvcc_version | sed 's/\([[^.]][[^.]]*\).*/\1/'` minor=`echo $nvcc_version | sed 's/[[^.]][[^.]]*.\([[^.,]][[^.,]]*\).*/\1/'` +echo "CUDA $major.$minor used" + +if test "$major" -lt 4; then + echo "CUDA $major.$minor not supported" +fi + if test "$major" -eq 4; then - if test "$minor" -ge 1; then - echo "CUDA $major.$minor used" - else - echo "CUDA $major.$minor used" + if test "$minor" -eq 0; then CUDA_VERSION="-DCUDA_4_0" fi -else - echo "CUDA $major.$minor not supported" fi AC_CONFIG_FILES([Makefile.cuda]) diff --git a/src/components/nvml/linux-nvml.c b/src/components/nvml/linux-nvml.c index a0c1f55..df259db 100644 --- a/src/components/nvml/linux-nvml.c +++ b/src/components/nvml/linux-nvml.c @@ -451,8 +451,9 @@ detectDevices( ) for (j=0; j < device_count; j++ ) { if ( !strncmp( busId, nvml_busIds[j], 16) ) { ret = nvmlDeviceGetHandleByIndex(j, &devices[i] ); - if ( NVML_SUCCESS != ret ) + if ( NVML_SUCCESS != ret ) { SUBDBG("nvmlDeviceGetHandleByIndex(%d, &devices[%d]) failed.\n", j, i); + } return PAPI_ESYS; break; } diff --git a/src/components/rapl/linux-rapl.c b/src/components/rapl/linux-rapl.c index 94d725c..d668697 100644 --- a/src/components/rapl/linux-rapl.c +++ b/src/components/rapl/linux-rapl.c @@ -314,6 +314,13 @@ _rapl_init_component( int cidx ) pp1_avail=0; dram_avail=1; } + else if (hw_info->cpuid_model==58) { + /* IvyBridge */ + package_avail=1; + pp0_avail=1; + pp1_avail=1; + dram_avail=0; + } else { /* not a supported model */ strncpy(_rapl_vector.cmp_info.disabled_reason, diff --git a/src/configure b/src/configure index 50b76ed..8d67554 100755 --- a/src/configure +++ b/src/configure @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.59 for PAPI 5.0.0.0. +# Generated by GNU Autoconf 2.59 for PAPI 5.0.1.0. # # Report bugs to . # @@ -269,8 +269,8 @@ SHELL=${CONFIG_SHELL-/bin/sh} # Identity of this package. PACKAGE_NAME='PAPI' PACKAGE_TARNAME='papi' -PACKAGE_VERSION='5.0.0.0' -PACKAGE_STRING='PAPI 5.0.0.0' +PACKAGE_VERSION='5.0.1.0' +PACKAGE_STRING='PAPI 5.0.1.0' PACKAGE_BUGREPORT='ptools-perfapi@eecs.utk.edu' ac_unique_file="papi.c" @@ -788,7 +788,7 @@ if test "$ac_init_help" = "long"; then # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures PAPI 5.0.0.0 to adapt to many kinds of systems. +\`configure' configures PAPI 5.0.1.0 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -845,7 +845,7 @@ fi if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of PAPI 5.0.0.0:";; + short | recursive ) echo "Configuration of PAPI 5.0.1.0:";; esac cat <<\_ACEOF @@ -998,7 +998,7 @@ fi test -n "$ac_init_help" && exit 0 if $ac_init_version; then cat <<\_ACEOF -PAPI configure 5.0.0.0 +PAPI configure 5.0.1.0 generated by GNU Autoconf 2.59 Copyright (C) 2003 Free Software Foundation, Inc. @@ -1012,7 +1012,7 @@ cat >&5 <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by PAPI $as_me 5.0.0.0, which was +It was created by PAPI $as_me 5.0.1.0, which was generated by GNU Autoconf 2.59. Invocation command line was $ $0 $@ @@ -5290,6 +5290,9 @@ fi echo "$as_me:$LINENO: result: $shlib" >&5 echo "${ECHO_T}$shlib" >&6 +# default +pfm_incdir="libpfm4/include" + ################################################## # perfctr ################################################## @@ -5358,6 +5361,7 @@ fi fi if test "$perfctr" != 0; then + pfm_incdir="libpfm-3.y/include/" echo "$as_me:$LINENO: checking for perfctr version" >&5 echo $ECHO_N "checking for perfctr version... $ECHO_C" >&6 if test "$perfctr" = 7 -a "$arch" != "ppc64"; then @@ -5403,11 +5407,11 @@ if test "$perfctr" != 0; then dotest=0 if test "x$perfctr_root" != "x"; then LIBS="-L$perfctr_root/usr.lib -lperfctr" - CPPFLAGS="-I$perfctr_root/usr.lib -I$perfctr_root/linux/include" + CPPFLAGS="$CPPFLAGS -I$perfctr_root/usr.lib -I$perfctr_root/linux/include" dotest=1 elif test "x$perfctr_prefix" != "x"; then LIBS="-L$perfctr_prefix/lib -lperfctr" - CPPFLAGS="-I$perfctr_prefix/include" + CPPFLAGS="$CPPFLAGS -I$perfctr_prefix/include" perfctr_libdir="$perfctr_prefix/lib" perfctr_incdir="$perfctr_prefix/include" dotest=1 @@ -5421,6 +5425,7 @@ if test "$perfctr" != 0; then dotest=1 fi fi + if test "$dotest" = 1; then echo "$as_me:$LINENO: checking for vperfctr_open in -lperfctr" >&5 echo $ECHO_N "checking for vperfctr_open in -lperfctr... $ECHO_C" >&6 @@ -5717,6 +5722,7 @@ if test "${with_perfmon+set}" = set; then perfmon=$withval user_specified_interface=perfmon force_perfmon2=yes + pfm_incdir="libpfm-3.y/include" perfmon=`echo ${perfmon} | sed 's/^ \t*//;s/ \t*$//'` perfmon=`echo ${perfmon} | grep -e '[1-9]\.[0-9][0-9]*'` if test "x$perfmon" = "x"; then @@ -5781,6 +5787,7 @@ fi fi if test "$perfmon" != 0; then + pfm_incdir="libpfm-3.y/include" perfmon=`echo ${perfmon} | sed 's/^ \t*//;s/ \t*$//'` perfmon=`echo ${perfmon} | grep -e '[1-9]\.[0-9][0-9]*'` perfmon=`echo ${perfmon} | sed 's/\.//'` @@ -5797,32 +5804,30 @@ fi fi; + + # Check whether --with-pfm_root or --without-pfm_root was given. if test "${with_pfm_root+set}" = set; then withval="$with_pfm_root" pfm_root=$withval - user_specified_interface=perfmon fi; # Check whether --with-pfm_prefix or --without-pfm_prefix was given. if test "${with_pfm_prefix+set}" = set; then withval="$with_pfm_prefix" pfm_prefix=$withval - user_specified_interface=perfmon fi; # Check whether --with-pfm_incdir or --without-pfm_incdir was given. if test "${with_pfm_incdir+set}" = set; then withval="$with_pfm_incdir" pfm_incdir=$withval - user_specified_interface=perfmon fi; # Check whether --with-pfm_libdir or --without-pfm_libdir was given. if test "${with_pfm_libdir+set}" = set; then withval="$with_pfm_libdir" pfm_libdir=$withval - user_specified_interface=perfmon fi; @@ -5831,7 +5836,7 @@ fi; ################################################## perf_events=no force_perf_events=no -pe_incdir="libpfm4/include/perfmon" +pe_incdir="$pfm_incdir/perfmon" # Check whether --with-perf_events or --without-perf_events was given. @@ -5952,11 +5957,11 @@ if test "$perfmon" != 0 -o "$perf_events" = "yes"; then dotest=0 if test "x$pfm_root" != "x"; then LIBS="-L$pfm_root/lib -lpfm" - CPPFLAGS="-I$pfm_root/include" + CPPFLAGS="$CPPFLAGS -I$pfm_root/include" dotest=1 elif test "x$pfm_prefix" != "x"; then LIBS="-L$pfm_prefix/lib -lpfm" - CPPFLAGS="-I$pfm_prefix/include" + CPPFLAGS="$CPPFLAGS -I$pfm_prefix/include" if test "x$pfm_libdir" = "x"; then pfm_libdir="$pfm_prefix/lib" fi @@ -5970,8 +5975,7 @@ if test "$perfmon" != 0 -o "$perf_events" = "yes"; then dotest=1 fi if test "x$pfm_incdir" != "x"; then - CPPFLAGS="-I$pfm_incdir" - dotest=1 + CPPFLAGS="$CPPFLAGS -I$pfm_incdir" fi fi if test "$dotest" = 1; then @@ -7955,7 +7959,7 @@ _ASBOX } >&5 cat >&5 <<_CSEOF -This file was extended by PAPI $as_me 5.0.0.0, which was +This file was extended by PAPI $as_me 5.0.1.0, which was generated by GNU Autoconf 2.59. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -8015,7 +8019,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -PAPI config.status 5.0.0.0 +PAPI config.status 5.0.1.0 configured by $0, generated by GNU Autoconf 2.59, with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\" diff --git a/src/configure.in b/src/configure.in index 6e79436..234b4fc 100644 --- a/src/configure.in +++ b/src/configure.in @@ -6,7 +6,7 @@ # cross compiling should work differently... AC_PREREQ(2.59) -AC_INIT(PAPI, 5.0.0.0, ptools-perfapi@eecs.utk.edu) +AC_INIT(PAPI, 5.0.1.0, ptools-perfapi@eecs.utk.edu) AC_CONFIG_SRCDIR([papi.c]) AC_CONFIG_HEADER([config.h]) @@ -766,6 +766,9 @@ if test "$papiLIBS" != "shared static"; then fi AC_MSG_RESULT($shlib) +# default +pfm_incdir="libpfm4/include" + ################################################## # perfctr ################################################## @@ -788,6 +791,7 @@ if test "$cross_compiling" = "no" ; then fi if test "$perfctr" != 0; then + pfm_incdir="libpfm-3.y/include/" AC_MSG_CHECKING(for perfctr version) if test "$perfctr" = 7 -a "$arch" != "ppc64"; then AC_MSG_ERROR([Perfctr 2.7.x only works on PPC64 machines. Patch kernel with 2.6.x.]) @@ -817,11 +821,11 @@ if test "$perfctr" != 0; then dotest=0 if test "x$perfctr_root" != "x"; then LIBS="-L$perfctr_root/usr.lib -lperfctr" - CPPFLAGS="-I$perfctr_root/usr.lib -I$perfctr_root/linux/include" + CPPFLAGS="$CPPFLAGS -I$perfctr_root/usr.lib -I$perfctr_root/linux/include" dotest=1 elif test "x$perfctr_prefix" != "x"; then LIBS="-L$perfctr_prefix/lib -lperfctr" - CPPFLAGS="-I$perfctr_prefix/include" + CPPFLAGS="$CPPFLAGS -I$perfctr_prefix/include" perfctr_libdir="$perfctr_prefix/lib" perfctr_incdir="$perfctr_prefix/include" dotest=1 @@ -835,6 +839,7 @@ if test "$perfctr" != 0; then dotest=1 fi fi + if test "$dotest" = 1; then AC_CHECK_LIB([perfctr], [vperfctr_open], [AC_CHECK_HEADERS([libperfctr.h], @@ -871,6 +876,7 @@ AC_ARG_WITH(perfmon, [perfmon=$withval user_specified_interface=perfmon force_perfmon2=yes + pfm_incdir="libpfm-3.y/include" perfmon=`echo ${perfmon} | sed 's/^[ \t]*//;s/[ \t]*$//'` perfmon=`echo ${perfmon} | grep -e '[[1-9]]\.[[0-9]][[0-9]]*'` if test "x$perfmon" = "x"; then @@ -892,6 +898,7 @@ AC_ARG_WITH(perfmon, [perfmon=`cat /proc/perfmon | grep version | cut -d: -f2`], [perfmon=0])]) if test "$perfmon" != 0; then + pfm_incdir="libpfm-3.y/include" perfmon=`echo ${perfmon} | sed 's/^[ \t]*//;s/[ \t]*$//'` perfmon=`echo ${perfmon} | grep -e '[[1-9]]\.[[0-9]][[0-9]]*'` perfmon=`echo ${perfmon} | sed 's/\.//'` @@ -906,22 +913,20 @@ AC_ARG_WITH(perfmon, fi fi]) + + AC_ARG_WITH(pfm_root, [ --with-pfm-root= Specify path to source tree (for use by developers only) ], - [pfm_root=$withval - user_specified_interface=perfmon]) + [pfm_root=$withval]) AC_ARG_WITH(pfm_prefix, [ --with-pfm-prefix= Specify prefix to installed pfm distribution ], - [pfm_prefix=$withval - user_specified_interface=perfmon]) + [pfm_prefix=$withval]) AC_ARG_WITH(pfm_incdir, [ --with-pfm-incdir= Specify directory of pfm header files in non-standard location ], - [pfm_incdir=$withval - user_specified_interface=perfmon]) + [pfm_incdir=$withval]) AC_ARG_WITH(pfm_libdir, [ --with-pfm-libdir= Specify directory of pfm library in non-standard location ], - [pfm_libdir=$withval - user_specified_interface=perfmon]) + [pfm_libdir=$withval]) ################################################## @@ -929,7 +934,7 @@ AC_ARG_WITH(pfm_libdir, ################################################## perf_events=no force_perf_events=no -pe_incdir="libpfm4/include/perfmon" +pe_incdir="$pfm_incdir/perfmon" AC_ARG_WITH(perf_events, [ --with-perf-events Specify use of Linux Performance Event (requires kernel 2.6.32 or greater)], @@ -1001,11 +1006,11 @@ if test "$perfmon" != 0 -o "$perf_events" = "yes"; then dotest=0 if test "x$pfm_root" != "x"; then LIBS="-L$pfm_root/lib -lpfm" - CPPFLAGS="-I$pfm_root/include" + CPPFLAGS="$CPPFLAGS -I$pfm_root/include" dotest=1 elif test "x$pfm_prefix" != "x"; then LIBS="-L$pfm_prefix/lib -lpfm" - CPPFLAGS="-I$pfm_prefix/include" + CPPFLAGS="$CPPFLAGS -I$pfm_prefix/include" if test "x$pfm_libdir" = "x"; then pfm_libdir="$pfm_prefix/lib" fi @@ -1019,8 +1024,7 @@ if test "$perfmon" != 0 -o "$perf_events" = "yes"; then dotest=1 fi if test "x$pfm_incdir" != "x"; then - CPPFLAGS="-I$pfm_incdir" - dotest=1 + CPPFLAGS="$CPPFLAGS -I$pfm_incdir" fi fi if test "$dotest" = 1; then diff --git a/src/libpfm4/Makefile b/src/libpfm4/Makefile index 12d9c17..440249f 100644 --- a/src/libpfm4/Makefile +++ b/src/libpfm4/Makefile @@ -76,6 +76,9 @@ tags: @echo creating tags $(MAKE) -C lib $@ -.PHONY: all clean distclean depend tar install install_examples lib +static: + make all CONFIG_PFMLIB_SHARED=n + +.PHONY: all clean distclean depend tar install install_examples lib static # DO NOT DELETE diff --git a/src/libpfm4/README b/src/libpfm4/README index ddef1aa..5774890 100644 --- a/src/libpfm4/README +++ b/src/libpfm4/README @@ -52,6 +52,7 @@ The library supports many PMUs. The current version can handle: - For ARM: ARMV7 Cortex A8 ARMV7 Cortex A9 + ARMV7 Cortex A15 - For SPARC Ultra I, II diff --git a/src/libpfm4/config.mk b/src/libpfm4/config.mk index e351314..29d848f 100644 --- a/src/libpfm4/config.mk +++ b/src/libpfm4/config.mk @@ -95,7 +95,7 @@ endif # Library version # VERSION=4 -REVISION=2 +REVISION=3 AGE=0 # @@ -181,16 +181,17 @@ PFMLIBDIR=$(TOPDIR)/lib # -Wextra: to enable extra compiler sanity checks (e.g., signed vs. unsigned) # -Wno-unused-parameter: to avoid warnings on unused foo(void *this) parameter # +DBG?=-g -Wall -Werror -Wextra -Wno-unused-parameter + ifeq ($(SYS),Darwin) # older gcc-4.2 does not like -Wextra and some of our initialization code DBG?=-g -Wall -Werror LDCONFIG=true -else -ifeq (icc,$(findstring icc,$(CC))) -DBG?=-g -Wall -Werror -Wextra -else -DBG?=-g -Wall -Werror -Wextra -Wno-unused-parameter endif + +ifeq ($(SYS),FreeBSD) +# gcc-4.2 does not like -Wextra and some of our initialization code +DBG=-g -Wall -Werror endif CFLAGS+=$(OPTIM) $(DBG) -I$(SYSINCDIR) -I$(PFMINCDIR) diff --git a/src/libpfm4/debian/changelog b/src/libpfm4/debian/changelog index bff2982..ff721b6 100644 --- a/src/libpfm4/debian/changelog +++ b/src/libpfm4/debian/changelog @@ -1,3 +1,22 @@ +libpfm4 (3.0) unstable; urgency=low + + * ARM Cortex A15 support + * updated Intel Sandy Bridge core PMU events + * Intel Sandy Bridge desktop (model 42) uncore PMU support + * Intel Ivy Bridge support + * full perf_events generic event support + * updated perf_examples + * enabled Intel Nehalem/Westmere uncore PMU support + * AMD LLano processor supoprt (Fam 12h) + * AMD Turion rocessor supoprt (Fam 11h) + * Intel Atom Cedarview processor support + * Win32 compilation support + * perf_events excl attribute + * perf_events generic hw event aliases support + * many bug fixes + + -- Stephane Eranian Mon, 27 Aug 2012 17:45:22 +0200 + libpfm4 (2.0) unstable; urgency=low * updated event tables for Intel X86 processors diff --git a/src/libpfm4/debian/rules b/src/libpfm4/debian/rules index 765ba4a..abe2de9 100755 --- a/src/libpfm4/debian/rules +++ b/src/libpfm4/debian/rules @@ -20,7 +20,7 @@ override_dh_auto_install: build dh_testroot dh_prep dh_installdirs - make install DESTDIR=$(CURDIR)/debian/tmp PREFIX=/usr CONFIG_PFMLIB_NOPYTHON=n + make install DESTDIR=$(CURDIR)/debian/tmp PREFIX=/usr CONFIG_PFMLIB_NOPYTHON=n LDCONFIG=true %: dh $@ diff --git a/src/libpfm4/docs/Makefile b/src/libpfm4/docs/Makefile index 9534e4f..dcbf414 100644 --- a/src/libpfm4/docs/Makefile +++ b/src/libpfm4/docs/Makefile @@ -41,7 +41,17 @@ ARCH_MAN=libpfm_intel_core.3 \ libpfm_intel_nhm_unc.3 \ libpfm_intel_wsm.3 \ libpfm_intel_wsm_unc.3 \ - libpfm_intel_snb.3 + libpfm_intel_snb.3 \ + libpfm_intel_snb_unc.3 \ + libpfm_intel_ivb.3 \ + libpfm_intel_snbep_unc_cbo.3 \ + libpfm_intel_snbep_unc_ha.3 \ + libpfm_intel_snbep_unc_imc.3 \ + libpfm_intel_snbep_unc_pcu.3 \ + libpfm_intel_snbep_unc_qpi.3 \ + libpfm_intel_snbep_unc_ubo.3 \ + libpfm_intel_snbep_unc_r2pcie.3 \ + libpfm_intel_snbep_unc_r3qpi.3 ifeq ($(CONFIG_PFMLIB_ARCH_I386),y) ARCH_MAN += libpfm_intel_p6.3 libpfm_intel_coreduo.3 @@ -49,6 +59,11 @@ endif endif +ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) +ARCH_MAN += libpfm_arm_ac15.3 libpfm_arm_ac8.3 libpfm_arm_ac9.3 +endif + + ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y) ARCH_MAN += libpfm_mips_74k.3 endif diff --git a/src/libpfm4/docs/man3/libpfm_arm_ac15.3 b/src/libpfm4/docs/man3/libpfm_arm_ac15.3 new file mode 100644 index 0000000..0ecabce --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_arm_ac15.3 @@ -0,0 +1,35 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_arm_ac15 - support for Arm Cortex A15 PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: arm_ac15 +.B PMU desc: ARM Cortex A15 +.sp +.SH DESCRIPTION +The library supports the ARM Cortex A15 core PMU. + +This PMU supports 6 counters and privilege levels filtering. + +.SH MODIFIERS +The following modifiers are supported on ARM Cortex A15: +.TP +.B u +Measure at the user level. This corresponds to \fBPFM_PLM3\fR. +This is a boolean modifier. +.TP +.B k +Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. +This is a boolean modifier. +.TP +.B hv +Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. +This is a boolean modifier. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_arm_ac8.3 b/src/libpfm4/docs/man3/libpfm_arm_ac8.3 new file mode 100644 index 0000000..cb845a0 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_arm_ac8.3 @@ -0,0 +1,21 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_arm_ac8 - support for ARM Cortex A8 PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: arm_ac8 +.B PMU desc: ARM Cortex A8 +.sp +.SH DESCRIPTION +The library supports the ARM Cortex A8 core PMU. + +This PMU supports 2 counters and has no privilege levels filtering. +No event modifiers are available. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_arm_ac9.3 b/src/libpfm4/docs/man3/libpfm_arm_ac9.3 new file mode 100644 index 0000000..8c8e03f --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_arm_ac9.3 @@ -0,0 +1,21 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_arm_ac9 - support for ARM Cortex A9 PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: arm_ac9 +.B PMU desc: ARM Cortex A9 +.sp +.SH DESCRIPTION +The library supports the ARM Cortex A9 core PMU. + +This PMU supports 2 counters and has no privilege levels filtering. +No event modifiers are available. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_ivb.3 b/src/libpfm4/docs/man3/libpfm_intel_ivb.3 index 816ee0b..72cfab3 100644 --- a/src/libpfm4/docs/man3/libpfm_intel_ivb.3 +++ b/src/libpfm4/docs/man3/libpfm_intel_ivb.3 @@ -1,4 +1,4 @@ -.TH LIBPFM 3 "June, 2012" "" "Linux Programmer's Manual" +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_ivb - support for Intel Ivy Bridge core PMU .SH SYNOPSIS @@ -10,11 +10,10 @@ libpfm_intel_ivb - support for Intel Ivy Bridge core PMU .sp .SH DESCRIPTION The library supports the Intel Ivy Bridge core PMU. It should be noted that -this PMU model only covers the each core's PMU and not the socket level -PMU. This PMU model covers only th single socket Ivyy Bridge processors, a.k.a., -Intel Core I3/I5/I7 3xxx series. +this PMU model only covers each core's PMU and not the socket level +PMU. -On Ivyy Bridge, the number of generic counters depends on the Hyperthreading (HT) mode. +On Ivy Bridge, the number of generic counters depends on the Hyperthreading (HT) mode. When HT is on, then only 4 generic counters are available. When HT is off, then 8 generic counters are available. The \fBpfm_get_pmu_info()\fR function returns the maximum number of generic counters in \fBnum_cntrs\fr. @@ -48,12 +47,11 @@ modifier with values in the range [0:255]. Measure on both threads at the same time assuming hyper-threading is enabled. This is a boolean modifier. .SH OFFCORE_RESPONSE events -Intel Ivy Bridge provides two offcore_response events, like Intel Westmere. -They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. +Intel Ivy Bridge provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. -Those events needs special treatment in the performance monitoring infrastructure +Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in -case an offcore_response event is monitored simultaneously, the kernel needs +case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal events by the library. The extra diff --git a/src/libpfm4/docs/man3/libpfm_intel_snb.3 b/src/libpfm4/docs/man3/libpfm_intel_snb.3 index 0310895..ae7c921 100644 --- a/src/libpfm4/docs/man3/libpfm_intel_snb.3 +++ b/src/libpfm4/docs/man3/libpfm_intel_snb.3 @@ -1,4 +1,4 @@ -.TH LIBPFM 3 "Janury, 2011" "" "Linux Programmer's Manual" +.TH LIBPFM 3 "January, 2011" "" "Linux Programmer's Manual" .SH NAME libpfm_intel_snb - support for Intel Sandy Bridge core PMU .SH SYNOPSIS @@ -12,9 +12,8 @@ libpfm_intel_snb - support for Intel Sandy Bridge core PMU .sp .SH DESCRIPTION The library supports the Intel Sandy Bridge core PMU. It should be noted that -this PMU model only covers the each core's PMU and not the socket level -PMU. This PMU model covers only th single socket Sandy Bridge processors, a.k.a., -Intel Core I7 2xxx series. +this PMU model only covers each core's PMU and not the socket level +PMU. For that refer to the Sandy Bridge uncore PMU support. On Sandy Bridge, the number of generic counters depends on the Hyperthreading (HT) mode. When HT is on, then only 4 generic counters are available. When HT is off, then 8 generic @@ -53,9 +52,9 @@ Measure on both threads at the same time assuming hyper-threading is enabled. Th Intel Sandy Bridge provides two offcore_response events, like Intel Westmere. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. -Those events needs special treatment in the performance monitoring infrastructure +Those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. Thus, in -case an offcore_response event is monitored simultaneously, the kernel needs +case multiple offcore_response events are monitored simultaneously, the kernel needs to manage the sharing of that extra register. The offcore_response events are exposed as a normal events by the library. The extra @@ -89,6 +88,9 @@ But the following are illegal: .TP .B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE +.SH SEE ALSO +libpfm_snb_unc(3) + .SH AUTHORS .nf Stephane Eranian diff --git a/src/libpfm4/docs/man3/libpfm_intel_snb_unc.3 b/src/libpfm4/docs/man3/libpfm_intel_snb_unc.3 new file mode 100644 index 0000000..9591832 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snb_unc.3 @@ -0,0 +1,48 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snb_unc - support for Intel Sandy Bridge uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snb_unc_cbo0, snb_unc_cbo1, snb_unc_cbo2, snb_unc_cbo3 +.B PMU desc: Intel Sandy Bridge C-box uncore +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge client part (model 42) uncore PMU. +The support is currently limited to the Coherency Box, so called C-Box for up +to 4 physical cores. + +Each physical core has an associated C-Box which it uses to communictate with +the L3 cache. The C-boxes all support the same set of events. However, Core 0 +C-box (snb_unc_cbo0) supports an additional uncore clock ticks event: \fBUNC_CLOCKTICKS\fR. + + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR +occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event +to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. +This is a boolean modifier. +.TP +.B c +Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles +in which the number of occurrences of the event is greater or equal to the threshold. This is an integer +modifier with values in the range [0:255]. + +.P +Both the \fBUNC_CBO_CACHE_LOOKUP\fR and \fBUNC_CBO_XSNP_RESPONSE\fR requires two umasks to be valid. +For \fBUNC_CBO_CACHE_LOOKUP\fR the first umask must be one of the MESI state umasks, the second has to be one +of the filters. For \fBUNC_CBO_XSNP_RESPONSE\fR the first umask must be one of the snoop types, the second +has to be one of the filters. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_cbo.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_cbo.3 new file mode 100644 index 0000000..24fd517 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_cbo.3 @@ -0,0 +1,72 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_cbo - support for Intel Sandy Bridge-EP C-Box uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_cbo[0-7] +.B PMU desc: Intel Sandy Bridge-EP C-Box uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge C-Box (coherency engine) uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There is one C-box +PMU per physical core. Therefore there are eight identical C-Box PMU instances +numbered frmo 0 to 7. On dual-socket systems, the number refers to the C-Box +PMU on the socket where the program runs. For instance, if running on CPU8, then +snbep_unc_cbo0 refers to the C-Box for physical core 0 on socket 1. Conversely, +if running on CPU0, then the same snbep_unc_cbo0 refers to the C-Box for physical +core 0 but on socket 0. + +Each C-Box PMU implements 4 generic counters and a filter register used only +with certain events and umasks. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count C-Box cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of C-Box cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.TP +.B nf +Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. +Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. +The node filter is an 8-bit max bitmask. A node corresponds to a processor +socket. The legal values therefore depdend on the underlying hardware configuration. For +dual-socket systems, the bitmask has two valid bits [0:1]. +.TP +.B cf +Core Filter. This is a 3-bit filter which is used to filter based on phyiscal core origin +of the C-Box request. Possible values are 0-7. If the filter is not specified, then no +filtering takes place. +.TP +.B tf +Thread Filter. This is a 1-bit filter which is used to filter C-Box requests based on logical +processor (hyper-thread) identification. Possibles values are 0-1. If the filter is not +specified, then no filtering takes place. + +.SH Opcode filtering + +Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction +type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. +Second, the opcode to match on must be selected via a second umasks amongs the OPC_* umasks. +For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO +transactions. + +Opcode matching may be combined with node filtering with certain umasks. In general the +filtering support is encoded into the umask name, e.g., NID_OPCODE supports both +node and opcode filtering. For instance, UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:nf=1. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_ha.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_ha.3 new file mode 100644 index 0000000..e63620f --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_ha.3 @@ -0,0 +1,35 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_ha - support for Intel Sandy Bridge-EP Home Agent (HA) uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_ha +.B PMU desc: Intel Sandy Bridge-EP HA uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge Home Agent (HA) uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There is only one +Home Agent per processor socket. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count HA cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of HA cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_imc.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_imc.3 new file mode 100644 index 0000000..2d37ba6 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_imc.3 @@ -0,0 +1,34 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_imc - support for Intel Sandy Bridge-EP Integrated Memory Controller (IMC) uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_imc[0-3] +.B PMU desc: Intel Sandy Bridge-EP IMC uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge Integrated Memory Controller (IMC) uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There are four IMC PMUs per socket. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count IMC cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of IMC cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_pcu.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_pcu.3 new file mode 100644 index 0000000..47ea498 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_pcu.3 @@ -0,0 +1,49 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_pcu - support for Intel Sandy Bridge-EP Power Controller Unit (PCU) uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_pcu +.B PMU desc: Intel Sandy Bridge-EP PCU uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge Power Controller Unit uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There is only one +PCU PMU per processor socket. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge C-Box uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count HA cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of HA cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:15]. +.TP +.B ff +Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. +The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be +multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are +counted. + +.SH Frequency band filtering + +There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, +UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into +a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the +encoding for each event individually because it processes events one at a time. The caller or the underlying kernel +interface may have to merge the band filter settings to program the filter register properly. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_qpi.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_qpi.3 new file mode 100644 index 0000000..dcaffa1 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_qpi.3 @@ -0,0 +1,35 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_qpi - support for Intel Sandy Bridge-EP QPI uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_qpi0, snbep_unc_qpi1 +.B PMU desc: Intel Sandy Bridge-EP QPI uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge Power QPI uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There are +two QPI PMUs per processor socket. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge QPI uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count QPI cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of QPI cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_r2pcie.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_r2pcie.3 new file mode 100644 index 0000000..d7486aa --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_r2pcie.3 @@ -0,0 +1,35 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_r2pcie - support for Intel Sandy Bridge-EP R2 PCIe uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_r2pcie +.B PMU desc: Intel Sandy Bridge-EP R2 PCIe uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge R2 PCIe uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There is only one R2PCIe PMU +per processor socket. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge R2PCIe uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count R2 PCIe cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of R2PCIe cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:15]. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_r3qpi.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_r3qpi.3 new file mode 100644 index 0000000..5f659d1 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_r3qpi.3 @@ -0,0 +1,35 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_r3qpi - support for Intel Sandy Bridge-EP R3QPI uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_r3qpi0, snbep_unc_r3qpi0 +.B PMU desc: Intel Sandy Bridge-EP R3QPI uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge R3QPI uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There are +two R3QPI PMUs per processor socket. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge R3PQI uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count R3QPI cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of R3QPI cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:15]. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_ubo.3 b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_ubo.3 new file mode 100644 index 0000000..afd246e --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_snbep_unc_ubo.3 @@ -0,0 +1,59 @@ +.TH LIBPFM 3 "August, 2012" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_snbep_unc_ubo - support for Intel Sandy Bridge-EP U-Box uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: snbep_unc_ubo +.B PMU desc: Intel Sandy Bridge-EP U-Box uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Sandy Bridge system configuration unit (U-Box) uncore PMU. +This PMU model only exists on Sandy Bridge model 45. There is only one U-Box PMU +per processor socket. + +.SH MODIFIERS +The following modifiers are supported on Intel Sandy Bridge U-Box uncore PMU: +.TP +.B i +Invert the meaning of the event. The counter will now count HA cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of HA cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:15]. +.TP +.B oi +Invert the meaning of the occupancy event POWER_STATE_OCCUPANCY. The counter will now count PCU cycles in which the +event is \fBnot\fR occurring. This is a boolean modifier +.TP +.B oe +Enable edge detection for the occupancy event POWER_STATE_OCCUPANCY. The event now counts only when there is a state +transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold +modifier (t) with a value greater or equal to one. This is a boolean modifier. + +.TP +.B ff +Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. +The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be +multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are +counted. + +.SH Frequency band filtering + +There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, +UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into +a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the +encoding for each event individually because it processes events one at a time. The caller or the underlying kernel +interface may have to merge the band filter settings to program the filter register properly. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/examples/showevtinfo.c b/src/libpfm4/examples/showevtinfo.c index 24ea546..3723da3 100644 --- a/src/libpfm4/examples/showevtinfo.c +++ b/src/libpfm4/examples/showevtinfo.c @@ -173,7 +173,9 @@ show_event_info_combo(pfm_event_info_t *info) pinfo.size = sizeof(pinfo); - pfm_get_pmu_info(info->pmu, &pinfo); + ret = pfm_get_pmu_info(info->pmu, &pinfo); + if (ret != PFM_SUCCESS) + errx(1, "cannot get PMU info"); ainfo = calloc(info->nattrs, sizeof(*ainfo)); if (!ainfo) @@ -647,7 +649,7 @@ static const struct attr_flags event_flags[]={ EVENT_FLAGS(NULL, 0, 0) }; - static void +static void parse_filters(char *arg) { const struct attr_flags *attr; diff --git a/src/libpfm4/include/perfmon/perf_event.h b/src/libpfm4/include/perfmon/perf_event.h index c0da39e..9c7f474 100644 --- a/src/libpfm4/include/perfmon/perf_event.h +++ b/src/libpfm4/include/perfmon/perf_event.h @@ -261,7 +261,7 @@ struct perf_event_mmap_page { uint64_t cap_usr_time:1, cap_usr_rdpmc:1, cap_____res:62; - }; + } SWIG_NAME(rdmap_cap); uint16_t pmc_width; uint16_t time_shift; uint32_t time_mult; diff --git a/src/libpfm4/include/perfmon/pfmlib.h b/src/libpfm4/include/perfmon/pfmlib.h index f823e81..5b1e263 100644 --- a/src/libpfm4/include/perfmon/pfmlib.h +++ b/src/libpfm4/include/perfmon/pfmlib.h @@ -149,6 +149,33 @@ typedef enum { PFM_PMU_AMD64_FAM12H_LLANO, /* AMD AMD64 Fam12h Llano */ PFM_PMU_AMD64_FAM11H_TURION, /* AMD AMD64 Fam11h Turion */ PFM_PMU_INTEL_IVB, /* Intel IvyBridge */ + PFM_PMU_ARM_CORTEX_A15, /* ARM Cortex A15 */ + + PFM_PMU_INTEL_SNB_UNC_CB0, /* Intel SandyBridge C-box 0 uncore PMU */ + PFM_PMU_INTEL_SNB_UNC_CB1, /* Intel SandyBridge C-box 1 uncore PMU */ + PFM_PMU_INTEL_SNB_UNC_CB2, /* Intel SandyBridge C-box 2 uncore PMU */ + PFM_PMU_INTEL_SNB_UNC_CB3, /* Intel SandyBridge C-box 3 uncore PMU */ + + PFM_PMU_INTEL_SNBEP_UNC_CB0, /* Intel SandyBridge-EP C-Box core 0 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_CB1, /* Intel SandyBridge-EP C-Box core 1 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_CB2, /* Intel SandyBridge-EP C-Box core 2 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_CB3, /* Intel SandyBridge-EP C-Box core 3 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_CB4, /* Intel SandyBridge-EP C-Box core 4 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_CB5, /* Intel SandyBridge-EP C-Box core 5 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_CB6, /* Intel SandyBridge-EP C-Box core 6 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_CB7, /* Intel SandyBridge-EP C-Box core 7 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_HA, /* Intel SandyBridge-EP HA uncore */ + PFM_PMU_INTEL_SNBEP_UNC_IMC0, /* Intel SandyBridge-EP IMC socket 0 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_IMC1, /* Intel SandyBridge-EP IMC socket 1 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_IMC2, /* Intel SandyBridge-EP IMC socket 2 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_IMC3, /* Intel SandyBridge-EP IMC socket 3 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_PCU, /* Intel SandyBridge-EP PCU uncore */ + PFM_PMU_INTEL_SNBEP_UNC_QPI0, /* Intel SandyBridge-EP QPI link 0 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_QPI1, /* Intel SandyBridge-EP QPI link 1 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_UBOX, /* Intel SandyBridge-EP U-Box uncore */ + PFM_PMU_INTEL_SNBEP_UNC_R2PCIE, /* Intel SandyBridge-EP R2PCIe uncore */ + PFM_PMU_INTEL_SNBEP_UNC_R3QPI0, /* Intel SandyBridge-EP R3QPI 0 uncore */ + PFM_PMU_INTEL_SNBEP_UNC_R3QPI1, /* Intel SandyBridge-EP R3QPI 1 uncore */ /* MUST ADD NEW PMU MODELS HERE */ PFM_PMU_MAX /* end marker */ diff --git a/src/libpfm4/lib/Makefile b/src/libpfm4/lib/Makefile index cda06b2..803b60c 100644 --- a/src/libpfm4/lib/Makefile +++ b/src/libpfm4/lib/Makefile @@ -48,15 +48,26 @@ ifeq ($(CONFIG_PFMLIB_ARCH_X86),y) ifeq ($(SYS),Linux) SRCS += pfmlib_intel_x86_perf_event.c pfmlib_amd64_perf_event.c \ - pfmlib_intel_netburst_perf_event.c + pfmlib_intel_netburst_perf_event.c \ + pfmlib_intel_snbep_unc_perf_event.c endif INCARCH = $(INC_X86) SRCS += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \ pfmlib_intel_x86_arch.c pfmlib_intel_atom.c \ pfmlib_intel_nhm_unc.c pfmlib_intel_nhm.c \ - pfmlib_intel_wsm.c pfmlib_intel_snb.c \ + pfmlib_intel_wsm.c \ + pfmlib_intel_snb.c pfmlib_intel_snb_unc.c \ pfmlib_intel_ivb.c \ + pfmlib_intel_snbep_unc.c \ + pfmlib_intel_snbep_unc_cbo.c \ + pfmlib_intel_snbep_unc_ha.c \ + pfmlib_intel_snbep_unc_imc.c \ + pfmlib_intel_snbep_unc_pcu.c \ + pfmlib_intel_snbep_unc_qpi.c \ + pfmlib_intel_snbep_unc_ubo.c \ + pfmlib_intel_snbep_unc_r2pcie.c \ + pfmlib_intel_snbep_unc_r3qpi.c \ pfmlib_intel_netburst.c \ pfmlib_amd64_k7.c pfmlib_amd64_k8.c pfmlib_amd64_fam10h.c \ pfmlib_amd64_fam11h.c pfmlib_amd64_fam12h.c \ @@ -179,7 +190,17 @@ INC_X86= pfmlib_intel_x86_priv.h \ events/intel_wsm_events.h \ events/intel_wsm_unc_events.h \ events/intel_snb_events.h \ - events/intel_ivb_events.h + events/intel_snb_unc_events.h \ + events/intel_ivb_events.h \ + pfmlib_intel_snbep_unc_priv.h \ + events/intel_snbep_unc_cbo_events.h \ + events/intel_snbep_unc_ha_events.h \ + events/intel_snbep_unc_imc_events.h \ + events/intel_snbep_unc_pcu_events.h \ + events/intel_snbep_unc_qpi_events.h \ + events/intel_snbep_unc_ubo_events.h \ + events/intel_snbep_unc_r2pcie_events.h \ + events/intel_snbep_unc_r3qpi_events.h INC_MIPS=events/mips_74k_events.h events/mips_74k_events.h @@ -205,6 +226,11 @@ INC_CELL=events/cell_events.h INC_ARM=events/arm_cortex_a8_events.h \ events/arm_cortex_a9_events.h +INC_ARM=pfmlib_arm_priv.h \ + events/arm_cortex_a8_events.h \ + events/arm_cortex_a9_events.h \ + events/arm_cortex_a15_events.h + INCDEP=$(INC_COMMON) $(INCARCH) all: $(TARGETS) diff --git a/src/libpfm4/lib/events/arm_cortex_a15_events.h b/src/libpfm4/lib/events/arm_cortex_a15_events.h new file mode 100644 index 0000000..25048fd --- /dev/null +++ b/src/libpfm4/lib/events/arm_cortex_a15_events.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * Contributed by Will Deacon + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Cortex A15 r2p0 + * based on Table 11-6 from the "Cortex A15 Technical Reference Manual" + */ +static const arm_entry_t arm_cortex_a15_pe[]={ + {.name = "SW_INCR", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x00, + .desc = "Instruction architecturally executed (condition check pass) Software increment" + }, + {.name = "L1I_CACHE_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x01, + .desc = "Level 1 instruction cache refill" + }, + {.name = "L1I_TLB_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x02, + .desc = "Level 1 instruction TLB refill" + }, + {.name = "L1D_CACHE_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x03, + .desc = "Level 1 data cache refill" + }, + {.name = "L1D_CACHE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x04, + .desc = "Level 1 data cache access" + }, + {.name = "L1D_TLB_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x05, + .desc = "Level 1 data TLB refill" + }, + + {.name = "INST_RETIRED", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x08, + .desc = "Instruction architecturally executed" + }, + {.name = "EXCEPTION_TAKEN", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x09, + .desc = "Exception taken" + }, + {.name = "EXCEPTION_RETURN", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x0a, + .desc = "Instruction architecturally executed (condition check pass) Exception return" + }, + {.name = "CID_WRITE_RETIRED", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x0b, + .desc = "Instruction architecturally executed (condition check pass) Write to CONTEXTIDR" + }, + + {.name = "BRANCH_MISPRED", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x10, + .desc = "Mispredicted or not predicted branch speculatively executed" + }, + {.name = "CPU_CYCLES", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x11, + .desc = "Cycles" + }, + {.name = "BRANCH_PRED", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x12, + .desc = "Predictable branch speculatively executed" + }, + {.name = "DATA_MEM_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x13, + .desc = "Data memory access" + }, + {.name = "L1I_CACHE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x14, + .desc = "Level 1 instruction cache access" + }, + {.name = "L1D_CACHE_WB", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x15, + .desc = "Level 1 data cache WriteBack" + }, + {.name = "L2D_CACHE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x16, + .desc = "Level 2 data cache access" + }, + {.name = "L2D_CACHE_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x17, + .desc = "Level 2 data cache refill" + }, + {.name = "L2D_CACHE_WB", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x18, + .desc = "Level 2 data cache WriteBack" + }, + {.name = "BUS_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x19, + .desc = "Bus access" + }, + {.name = "LOCAL_MEMORY_ERROR", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x1a, + .desc = "Local memory error" + }, + {.name = "INST_SPEC_EXEC", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x1b, + .desc = "Instruction speculatively executed" + }, + {.name = "TTBR_WRITE_RETIRED", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x1c, + .desc = "Instruction architecturally executed (condition check pass) Write to translation table base" + }, + {.name = "BUS_CYCLES", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x1d, + .desc = "Bus cycle" + }, + {.name = "L1D_READ_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x40, + .desc = "Level 1 data cache read access" + }, + {.name = "L1D_WRITE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x41, + .desc = "Level 1 data cache write access" + }, + {.name = "L1D_READ_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x42, + .desc = "Level 1 data cache read refill" + }, + {.name = "L1D_WRITE_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x43, + .desc = "Level 1 data cache write refill" + }, + {.name = "L1D_WB_VICTIM", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x46, + .desc = "Level 1 data cache writeback victim" + }, + {.name = "L1D_WB_CLEAN_COHERENCY", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x47, + .desc = "Level 1 data cache writeback cleaning and coherency" + }, + {.name = "L1D_INVALIDATE", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x48, + .desc = "Level 1 data cache invalidate" + }, + {.name = "L1D_TLB_READ_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x4c, + .desc = "Level 1 data TLB read refill" + }, + {.name = "L1D_TLB_WRITE_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x4d, + .desc = "Level 1 data TLB write refill" + }, + {.name = "L2D_READ_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x50, + .desc = "Level 2 data cache read access" + }, + {.name = "L2D_WRITE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x51, + .desc = "Level 2 data cache write access" + }, + {.name = "L2D_READ_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x52, + .desc = "Level 2 data cache read refill" + }, + {.name = "L2D_WRITE_REFILL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x53, + .desc = "Level 2 data cache write refill" + }, + {.name = "L2D_WB_VICTIM", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x56, + .desc = "Level 2 data cache writeback victim" + }, + {.name = "L2D_WB_CLEAN_COHERENCY", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x57, + .desc = "Level 2 data cache writeback cleaning and coherency" + }, + {.name = "L2D_INVALIDATE", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x58, + .desc = "Level 2 data cache invalidate" + }, + {.name = "BUS_READ_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x60, + .desc = "Bus read access" + }, + {.name = "BUS_WRITE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x61, + .desc = "Bus write access" + }, + {.name = "BUS_NORMAL_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x62, + .desc = "Bus normal access" + }, + {.name = "BUS_NOT_NORMAL_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x63, + .desc = "Bus not normal access" + }, + {.name = "BUS_NORMAL_ACCESS_2", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x64, + .desc = "Bus normal access" + }, + {.name = "BUS_PERIPH_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x65, + .desc = "Bus peripheral access" + }, + {.name = "DATA_MEM_READ_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x66, + .desc = "Data memory read access" + }, + {.name = "DATA_MEM_WRITE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x67, + .desc = "Data memory write access" + }, + {.name = "UNALIGNED_READ_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x68, + .desc = "Unaligned read access" + }, + {.name = "UNALIGNED_WRITE_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x69, + .desc = "Unaligned read access" + }, + {.name = "UNALIGNED_ACCESS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x6a, + .desc = "Unaligned access" + }, + {.name = "INST_SPEC_EXEC_LDREX", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x6c, + .desc = "LDREX exclusive instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_STREX_PASS", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x6d, + .desc = "STREX pass exclusive instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_STREX_FAIL", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x6e, + .desc = "STREX fail exclusive instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_LOAD", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x70, + .desc = "Load instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_STORE", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x71, + .desc = "Store instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_LOAD_STORE", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x72, + .desc = "Load or store instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_INTEGER_INST", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x73, + .desc = "Integer data processing instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_SIMD", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x74, + .desc = "Advanced SIMD instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_VFP", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x75, + .desc = "VFP instruction speculatively executed" + }, + {.name = "INST_SPEC_EXEC_SOFT_PC", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x76, + .desc = "Software of the PC instruction speculatively executed" + }, + {.name = "BRANCH_SPEC_EXEC_IMM_BRANCH", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x78, + .desc = "Immediate branch speculatively executed" + }, + {.name = "BRANCH_SPEC_EXEC_RET", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x79, + .desc = "Return branch speculatively executed" + }, + {.name = "BRANCH_SPEC_EXEC_IND", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x7a, + .desc = "Indirect branch speculatively executed" + }, + {.name = "BARRIER_SPEC_EXEC_ISB", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x7c, + .desc = "ISB barrier speculatively executed" + }, + {.name = "BARRIER_SPEC_EXEC_DSB", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x7d, + .desc = "DSB barrier speculatively executed" + }, + {.name = "BARRIER_SPEC_EXEC_DMB", + .modmsk = ARMV7_A15_ATTRS, + .code = 0x7e, + .desc = "DMB barrier speculatively executed" + }, +}; diff --git a/src/libpfm4/lib/events/intel_ivb_events.h b/src/libpfm4/lib/events/intel_ivb_events.h index f9a6d5e..f14d606 100644 --- a/src/libpfm4/lib/events/intel_ivb_events.h +++ b/src/libpfm4/lib/events/intel_ivb_events.h @@ -72,7 +72,7 @@ static const intel_x86_umask_t ivb_br_inst_exec[]={ .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, - { .uname = "TAKEN_RETURN_NEAR", + { .uname = "TAKEN_NEAR_RETURN", .udesc = "All taken indirect branches that have a return mnemonic", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, @@ -92,7 +92,7 @@ static const intel_x86_umask_t ivb_br_inst_exec[]={ .ucode = 0xff00, .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, }, - { .uname = "ALL_CONDITIONAL", + { .uname = "ALL_COND", .udesc = "All macro conditional branch instructions", .ucode = 0xc100, .uflags= INTEL_X86_NCOMBO, @@ -100,7 +100,7 @@ static const intel_x86_umask_t ivb_br_inst_exec[]={ { .uname = "ANY_COND", .udesc = "All macro conditional branch instructions", .ucode = 0xc100, - .uequiv = "ALL_CONDITIONAL", + .uequiv = "ALL_COND", .uflags= INTEL_X86_NCOMBO, }, { .uname = "ANY_INDIRECT_JUMP_NON_CALL_RET", @@ -121,7 +121,7 @@ static const intel_x86_umask_t ivb_br_inst_retired[]={ .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, - { .uname = "CONDITIONAL", + { .uname = "COND", .udesc = "All taken and not taken macro conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, @@ -174,12 +174,12 @@ static const intel_x86_umask_t ivb_br_misp_exec[]={ .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, - { .uname = "NONTAKEN_RETURN_NEAR", + { .uname = "NONTAKEN_NEAR_RETURN", .udesc = "All non-taken mispredicted indirect branches that have a return mnemonic", .ucode = 0x4800, .uflags= INTEL_X86_NCOMBO, }, - { .uname = "TAKEN_RETURN_NEAR", + { .uname = "TAKEN_NEAR_RETURN", .udesc = "All taken mispredicted indirect branches that have a return mnemonic", .ucode = 0x8800, .uflags= INTEL_X86_NCOMBO, @@ -237,7 +237,7 @@ static const intel_x86_umask_t ivb_br_misp_retired[]={ .ucode = 0x400, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, }, - { .uname = "CONDITIONAL", + { .uname = "COND", .udesc = "All mispredicted macro conditional branch instructions (Precise Event)", .ucode = 0x100, .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, @@ -333,21 +333,44 @@ static const intel_x86_umask_t ivb_dsb_fill[]={ }; static const intel_x86_umask_t ivb_dtlb_load_misses[]={ - { .uname = "DEMAND_LD_MISS_CAUSES_A_WALK", + { .uname = "MISS_CAUSES_A_WALK", .udesc = "Demand load miss in all TLB levels which causes a page walk of any page size", .ucode = 0x8100, .uflags= INTEL_X86_NCOMBO, }, - { .uname = "DEMAND_LD_WALK_COMPLETED", + { .uname = "WALK_COMPLETED", .udesc = "Demand load miss in all TLB levels which causes a page walk that completes for any page size", .ucode = 0x8200, .uflags= INTEL_X86_NCOMBO, }, - { .uname = "DEMAND_LD_WALK_DURATION", + { .uname = "WALK_DURATION", .udesc = "Cycles PMH is busy with a walk due to demand loads", .ucode = 0x8400, .uflags= INTEL_X86_NCOMBO, }, + { .uname = "DEMAND_LD_MISS_CAUSES_A_WALK", + .udesc = "Demand load miss in all TLB levels which causes a page walk of any page size", + .ucode = 0x8100, + .uequiv = "MISS_CAUSES_A_WALK", + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DEMAND_LD_WALK_COMPLETED", + .udesc = "Demand load miss in all TLB levels which causes a page walk that completes for any page size", + .ucode = 0x8200, + .uequiv = "WALK_COMPLETED", + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DEMAND_LD_WALK_DURATION", + .udesc = "Cycles PMH is busy with a walk due to demand loads", + .ucode = 0x8400, + .uequiv = "WALK_DURATION", + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STLB_HIT", + .udesc = "Number of load operations that missed L1TLB but hit L2TLB", + .ucode = 0x15f, /* override event code */ + .uflags= INTEL_X86_NCOMBO | INTEL_X86_CODE_OVERRIDE, + }, }; static const intel_x86_umask_t ivb_dtlb_store_misses[]={ @@ -783,7 +806,7 @@ static const intel_x86_umask_t ivb_l2_rqsts[]={ .ucode = 0xc00, .uflags= INTEL_X86_NCOMBO, }, - { .uname = "RFO_HITS", + { .uname = "RFO_HIT", .udesc = "Store RFO requests that hit L2 cache", .ucode = 0x400, .uflags= INTEL_X86_NCOMBO, @@ -1527,6 +1550,57 @@ static const intel_x86_umask_t ivb_baclears[]={ }, }; +static const intel_x86_umask_t ivb_cycle_activity[]={ + { .uname = "CYCLES_L2_PENDING", + .udesc = "Cycles with pending L2 miss loads", + .ucode = 0x0100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CYCLES_L2_PENDING_CORE", + .udesc = "Cycles with pending L2 miss loads per core", + .uequiv = "CYCLES_L2_PENDING:t=1", + .ucode = 0x0100 | (0x1 << INTEL_X86_ANY_BIT) , + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CYCLES_LDM_PENDING", + .udesc = "Cycles with pending memory loads", + .ucode = 0x0200, + .ucntmsk= 0xf, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CYCLES_LDM_PENDING_CORE", + .udesc = "Cycles with pending memory loads per core", + .uequiv = "CYCLES_LDM_PENDING:t=1", + .ucntmsk= 0xf, + .ucode = 0x0200 | (0x1 << INTEL_X86_ANY_BIT) , + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CYCLES_L1D_PENDING", + .udesc = "Cycles with pending L1D load cache misses", + .ucode = 0x0800, + .ucntmsk= 0x2, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CYCLES_L1D_PENDING_CORE", + .udesc = "Cycles with pending L1D loads cache misses per core", + .uequiv = "CYCLES_L1D_PENDING:t=1", + .ucntmsk= 0x2, + .ucode = 0x0800 | (0x1 << INTEL_X86_ANY_BIT) , + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CYCLES_NO_EXECUTE", + .udesc = "Cycles of dispatch stalls", + .ucode = 0x0400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CYCLES_NO_EXECUTE_CORE", + .udesc = "Cycles of dispatch stalls per core", + .uequiv = "CYCLES_NO_EXECUTE:t=1", + .ucode = 0x0400 | (0x1 << INTEL_X86_ANY_BIT) , + .uflags = INTEL_X86_NCOMBO, + }, +}; + static const intel_x86_entry_t intel_ivb_pe[]={ { .name = "ARITH", .desc = "Counts arithmetic multiply operations", @@ -1617,7 +1691,7 @@ static const intel_x86_entry_t intel_ivb_pe[]={ .umasks = ivb_cpl_cycles, }, { .name = "CPU_CLK_UNHALTED", - .desc = "Cases when the core is unhalted at 100 Mhz", + .desc = "Cycles when processor is not in halted state", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x3c, @@ -1931,8 +2005,8 @@ static const intel_x86_entry_t intel_ivb_pe[]={ .ngrp = 1, .umasks = ivb_mem_load_uops_llc_hit_retired, }, -{ .name = "MEM_LOAD_UOPS_LLC_MISS", - .desc = "Load uops that missed LLC", +{ .name = "MEM_LOAD_UOPS_LLC_MISS_RETIRED", + .desc = "Load uops retired that missed the LLC", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0xd3, @@ -2039,6 +2113,15 @@ static const intel_x86_entry_t intel_ivb_pe[]={ .ngrp = 1, .umasks = ivb_resource_stalls, }, +{ .name = "CYCLE_ACTIVITY", + .desc = "Stalled cycles", + .modmsk = INTEL_V3_ATTRS, + .cntmsk = 0xff, + .code = 0xa3, + .numasks = LIBPFM_ARRAY_SIZE(ivb_cycle_activity), + .ngrp = 1, + .umasks = ivb_cycle_activity, +}, { .name = "ROB_MISC_EVENTS", .desc = "Reorder buffer events", .modmsk = INTEL_V3_ATTRS, diff --git a/src/libpfm4/lib/events/intel_snb_events.h b/src/libpfm4/lib/events/intel_snb_events.h index f1f9736..2c9b359 100644 --- a/src/libpfm4/lib/events/intel_snb_events.h +++ b/src/libpfm4/lib/events/intel_snb_events.h @@ -1765,7 +1765,7 @@ static const intel_x86_entry_t intel_snb_pe[]={ .umasks = snb_cpl_cycles, }, { .name = "CPU_CLK_UNHALTED", - .desc = "Cases when the core is unhalted at 100 Mhz", + .desc = "Cycles when processor is not in halted state", .modmsk = INTEL_V3_ATTRS, .cntmsk = 0xff, .code = 0x3c, diff --git a/src/libpfm4/lib/events/intel_snb_unc_events.h b/src/libpfm4/lib/events/intel_snb_unc_events.h new file mode 100644 index 0000000..8b58926 --- /dev/null +++ b/src/libpfm4/lib/events/intel_snb_unc_events.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: snb_unc (Intel Sandy Bridge uncore PMU) + */ + +static const intel_x86_umask_t snb_unc_cbo_xsnp_response[]={ + { .uname = "MISS", + .udesc = "Number of snoop misses", + .ucode = 0x100, + .grpid = 0, + }, + { .uname = "INVAL", + .udesc = "Number of snoop invalidates of a non-modified line", + .ucode = 0x200, + .grpid = 0, + }, + { .uname = "HIT", + .udesc = "Number of snoop hits of a non-modified line", + .ucode = 0x400, + .grpid = 0, + }, + { .uname = "HITM", + .udesc = "Number of snoop hits of a modified line", + .ucode = 0x800, + .grpid = 0, + }, + { .uname = "INVAL_M", + .udesc = "Number of snoop invalidates of a modified line", + .ucode = 0x1000, + .grpid = 0, + }, + { .uname = "ANY_SNP", + .udesc = "Number of snoops", + .ucode = 0x1f00, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "EXTERNAL_FILTER", + .udesc = "Filter on cross-core snoops initiated by this Cbox due to external snoop request", + .ucode = 0x2000, + .grpid = 1, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "XCORE_FILTER", + .udesc = "Filter on cross-core snoops initiated by this Cbox due to processor core memory request", + .ucode = 0x4000, + .grpid = 1, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "EVICTION_FILTER", + .udesc = "Filter on cross-core snoops initiated by this Cbox due to LLC eviction", + .ucode = 0x8000, + .grpid = 1, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snb_unc_cbo_cache_lookup[]={ + { .uname = "STATE_M", + .udesc = "Number of LLC lookup requests for a line in modified state", + .ucode = 0x100, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STATE_E", + .udesc = "Number of LLC lookup requests for a line in exclusive state", + .ucode = 0x200, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STATE_S", + .udesc = "Number of LLC lookup requests for a line in shared state", + .ucode = 0x400, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STATE_I", + .udesc = "Number of LLC lookup requests for a line in invalid state", + .ucode = 0x800, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STATE_MESI", + .udesc = "Number of LLC lookup requests for a line", + .ucode = 0xf00, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "READ_FILTER", + .udesc = "Filter on processor core initiated cacheable read requests", + .ucode = 0x1000, + .grpid = 1, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITE_FILTER", + .udesc = "Filter on processor core initiated cacheable write requests", + .ucode = 0x2000, + .grpid = 1, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "EXTSNP_FILTER", + .udesc = "Filter on external snoop requests", + .ucode = 0x4000, + .grpid = 1, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY_FILTER", + .udesc = "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests", + .ucode = 0x8000, + .grpid = 1, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snb_unc_arb_trk_occupancy[]={ + { .uname = "ALL", + .udesc = "Counts cycles weighted by the number of requests waiting for data returning from the memory controller, (includes coherent and non-coherent requests initiated by cores, processor graphic units, or LLC)", + .ucode = 0x100, + .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snb_unc_arb_trk[]={ + { .uname = "ALL", + .udesc = "Counts number of coherent and in-coherent requests initiated by cores, processor graphic units, or LLC", + .ucode = 0x100, + .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "WRITES", + .udesc = "Counts the number of allocated write entries, include full, partial, and LLC evictions", + .ucode = 0x2000, + .uflags= INTEL_X86_NCOMBO, + }, + { .uname = "EVICTIONS", + .udesc = "Counts the number of LLC evictions allocated", + .ucode = 0x8000, + .uflags= INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snb_unc_arb_coh_trk_occupancy[]={ + { .uname = "ALL", + .udesc = "Cycles weighted by number of requests pending in Coherency Tracker", + .ucode = 0x100, + .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snb_unc_arb_coh_trk_request[]={ + { .uname = "ALL", + .udesc = "Number of requests allocated in Coherency Tracker", + .ucode = 0x100, + .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_entry_t intel_snb_unc_cbo0_pe[]={ +{ .name = "UNC_CLOCKTICKS", + .desc = "uncore clock ticks", + .cntmsk = 1ULL << 32, + .code = 0xff, /* perf_event pseudo encoding */ + .flags = INTEL_X86_FIXED, +}, +{ .name = "UNC_CBO_XSNP_RESPONSE", + .desc = "Snoop responses", + .modmsk = INTEL_SNB_UNC_ATTRS, + .cntmsk = 0xff, + .code = 0x22, + .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_xsnp_response), + .ngrp = 2, + .umasks = snb_unc_cbo_xsnp_response, +}, +{ .name = "UNC_CBO_CACHE_LOOKUP", + .desc = "LLC cache lookups", + .modmsk = INTEL_SNB_UNC_ATTRS, + .cntmsk = 0xff, + .code = 0x34, + .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_cache_lookup), + .ngrp = 2, + .umasks = snb_unc_cbo_cache_lookup, +}, +}; + +static const intel_x86_entry_t intel_snb_unc_cbo_pe[]={ +{ .name = "UNC_CBO_XSNP_RESPONSE", + .desc = "Snoop responses (must provide a snoop type and filter)", + .modmsk = INTEL_SNB_UNC_ATTRS, + .cntmsk = 0xff, + .code = 0x22, + .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_xsnp_response), + .ngrp = 2, + .umasks = snb_unc_cbo_xsnp_response, +}, +{ .name = "UNC_CBO_CACHE_LOOKUP", + .desc = "LLC cache lookups", + .modmsk = INTEL_SNB_UNC_ATTRS, + .cntmsk = 0xff, + .code = 0x34, + .numasks = LIBPFM_ARRAY_SIZE(snb_unc_cbo_cache_lookup), + .ngrp = 2, + .umasks = snb_unc_cbo_cache_lookup, +}, +}; + +static const intel_x86_entry_t intel_snb_unc_arb_pe[]={ +{ .name = "UNC_ARB_TRK_OCCUPANCY", + .desc = "ARB tracker occupancy", + .modmsk = INTEL_SNB_UNC_ATTRS, + .cntmsk = 0x1, + .code = 0x80, + .numasks = LIBPFM_ARRAY_SIZE(snb_unc_arb_trk_occupancy), + .ngrp = 1, + .umasks = snb_unc_arb_trk_occupancy, +}, +{ .name = "UNC_ARB_COH_TRK_OCCUPANCY", + .desc = "Coherency traffic occupancy", + .modmsk = INTEL_SNB_UNC_ATTRS, + .cntmsk = 0x1, + .code = 0x83, + .flags= INTEL_X86_PEBS, + .numasks = LIBPFM_ARRAY_SIZE(snb_unc_arb_coh_trk_occupancy), + .ngrp = 1, + .umasks = snb_unc_arb_coh_trk_occupancy, +}, +{ .name = "UNC_ARB_COH_TRK_REQUEST", + .desc = "Coherency traffic requests", + .modmsk = INTEL_SNB_UNC_ATTRS, + .cntmsk = 0x1, + .code = 0x84, + .numasks = LIBPFM_ARRAY_SIZE(snb_unc_arb_coh_trk_request), + .ngrp = 1, + .umasks = snb_unc_arb_coh_trk_request, +}, +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_cbo_events.h b/src/libpfm4/lib/events/intel_snbep_unc_cbo_events.h new file mode 100644 index 0000000..7161a89 --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_cbo_events.h @@ -0,0 +1,792 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: snbep_unc_cbo (Intel SandyBridge-EP C-Box uncore PMU) + */ + +#define CBO_FILT_MESIF(a, b, c, d) \ + { .uname = "STATE_"#a,\ + .udesc = #b" cacheline state",\ + .ucode = 1ULL << (32 + 18 + (c)),\ + .grpid = d, \ + } + +#define CBO_FILT_MESIFS(d) \ + CBO_FILT_MESIF(I, Invalid, 0, d), \ + CBO_FILT_MESIF(S, Shared, 1, d), \ + CBO_FILT_MESIF(E, Exclusive, 2, d), \ + CBO_FILT_MESIF(M, Modified, 3, d), \ + CBO_FILT_MESIF(F, Forward, 4, d), \ + { .uname = "STATE_MESIF",\ + .udesc = "Any cache line state",\ + .ucode = 0x1fULL << (32 + 18),\ + .grpid = d, \ + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, \ + } + +#define CBO_FILT_OPC(d) \ + { .uname = "OPC_RFO",\ + .udesc = "Demand data RFO (combine with any OPCODE umask)",\ + .ucode = 0x180ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_CRD",\ + .udesc = "Demand code read (combine with any OPCODE umask)",\ + .ucode = 0x181ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_DRD",\ + .udesc = "Demand data read (combine with any OPCODE umask)",\ + .ucode = 0x182ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PRD",\ + .udesc = "Partial reads (UC) (combine with any OPCODE umask)",\ + .ucode = 0x187ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_WCILF",\ + .udesc = "Full Stream store (combine with any OPCODE umask)", \ + .ucode = 0x18cULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_WCIL",\ + .udesc = "Partial Stream store (combine with any OPCODE umask)", \ + .ucode = 0x18dULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PF_RFO",\ + .udesc = "Prefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ + .ucode = 0x190ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PF_CODE",\ + .udesc = "Prefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ + .ucode = 0x191ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PF_DATA",\ + .udesc = "Prefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ + .ucode = 0x192ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PCIWILF",\ + .udesc = "PCIe write (non-allocating) (combine with any OPCODE umask)", \ + .ucode = 0x194ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PCIPRD",\ + .udesc = "PCIe UC read (combine with any OPCODE umask)", \ + .ucode = 0x195ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PCIITOM",\ + .udesc = "PCIe write (allocating) (combine with any OPCODE umask)", \ + .ucode = 0x19cULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PCIRDCUR",\ + .udesc = "PCIe read current (combine with any OPCODE umask)", \ + .ucode = 0x19eULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_WBMTOI",\ + .udesc = "Request writeback modified invalidate line (combine with any OPCODE umask)", \ + .ucode = 0x1c4ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_WBMTOE",\ + .udesc = "Request writeback modified set to exclusive (combine with any OPCODE umask)", \ + .ucode = 0x1c5ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_ITOM",\ + .udesc = "Request invalidate line (combine with any OPCODE umask)", \ + .ucode = 0x1c8ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PCINSRD",\ + .udesc = "PCIe non-snoop read (combine with any OPCODE umask)", \ + .ucode = 0x1e4ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PCINSWR",\ + .udesc = "PCIe non-snoop write (partial) (combine with any OPCODE umask)", \ + .ucode = 0x1e5ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + }, \ + { .uname = "OPC_PCINSWRF",\ + .udesc = "PCIe non-snoop write (full) (combine with any OPCODE umask)", \ + .ucode = 0x1e6ULL << (32 + 23), \ + .uflags = INTEL_X86_NCOMBO, \ + .grpid = d, \ + } + +static const intel_x86_umask_t snbep_unc_c_llc_lookup[]={ + { .uname = "DATA_READ", + .udesc = "Data read requests", + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + .ucode = 0x300, + }, + { .uname = "WRITE", + .udesc = "Write requests. Includes all write transactions (cached, uncached)", + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + .ucode = 0x500, + }, + { .uname = "REMOTE_SNOOP", + .udesc = "External snoop request", + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + .ucode = 0x900, + }, + { .uname = "NID", + .udesc = "Match a given RTID destination NID", + .uflags = INTEL_X86_NCOMBO, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .grpid = 0, + .ucode = 0x4100, + }, + CBO_FILT_MESIFS(1), +}; + +static const intel_x86_umask_t snbep_unc_c_llc_victims[]={ + { .uname = "M_STATE", + .udesc = "Lines in M state", + .ucode = 0x100, + }, + { .uname = "E_STATE", + .udesc = "Lines in E state", + .ucode = 0x200, + }, + { .uname = "S_STATE", + .udesc = "Lines in S state", + .ucode = 0x400, + }, + { .uname = "MISS", + .udesc = "TBD", + .ucode = 0x800, + }, + { .uname = "NID", + .udesc = "Victimized Lines matching the NID filter", + .ucode = 0x4000, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_misc[]={ + { .uname = "RSPI_WAS_FSE", + .udesc = "Silent snoop eviction", + .ucode = 0x100, + }, + { .uname = "WC_ALIASING", + .udesc = "Write combining aliasing", + .ucode = 0x200, + }, + { .uname = "STARTED", + .udesc = "TBD", + .ucode = 0x400, + }, + { .uname = "RFO_HIT_S", + .udesc = "RFO hits in S state", + .ucode = 0x800, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_ring_ad_used[]={ + { .uname = "UP_EVEN", + .udesc = "Up and Even ring polarity filter", + .ucode = 0x100, + }, + { .uname = "UP_ODD", + .udesc = "Up and odd ring polarity filter", + .ucode = 0x200, + }, + { .uname = "DOWN_EVEN", + .udesc = "Down and even ring polarity filter", + .ucode = 0x400, + }, + { .uname = "DOWN_ODD", + .udesc = "Down and odd ring polarity filter", + .ucode = 0x800, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_ring_bounces[]={ + { .uname = "AK_CORE", + .udesc = "Acknowledgment to core", + .ucode = 0x200, + }, + { .uname = "BL_CORE", + .udesc = "Data response to core", + .ucode = 0x400, + }, + { .uname = "IV_CORE", + .udesc = "Snoops of processor cache", + .ucode = 0x800, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_ring_iv_used[]={ + { .uname = "ANY", + .udesc = "Any filter", + .ucode = 0xf00, + .uflags = INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_rxr_ext_starved[]={ + { .uname = "IRQ", + .udesc = "Irq externally starved, therefore blocking the IPQ", + .ucode = 0x100, + }, + { .uname = "IPQ", + .udesc = "IPQ externally starved, therefore blocking the IRQ", + .ucode = 0x200, + }, + { .uname = "ISMQ", + .udesc = "ISMQ externally starved, therefore blocking both IRQ and IPQ", + .ucode = 0x400, + }, + { .uname = "ISMQ_BIDS", + .udesc = "Number of time the ISMQ bids", + .ucode = 0x800, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_rxr_inserts[]={ + { .uname = "IPQ", + .udesc = "IPQ", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ", + .udesc = "IRQ", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_REJECTED", + .udesc = "IRQ rejected", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VFIFO", + .udesc = "Counts the number of allocated into the IRQ ordering FIFO", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_rxr_ipq_retry[]={ + { .uname = "ADDR_CONFLICT", + .udesc = "Address conflict", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY", + .udesc = "Any Reject", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "FULL", + .udesc = "No Egress credits", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "QPI_CREDITS", + .udesc = "No QPI credits", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_rxr_irq_retry[]={ + { .uname = "ADDR_CONFLICT", + .udesc = "Address conflict", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY", + .udesc = "Any reject", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "FULL", + .udesc = "No Egress credits", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "QPI_CREDITS", + .udesc = "No QPI credits", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RTID", + .udesc = "No RTIDs", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_rxr_ismq_retry[]={ + { .uname = "ANY", + .udesc = "Any reject", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "FULL", + .udesc = "No Egress credits", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IIO_CREDITS", + .udesc = "No IIO credits", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "QPI_CREDITS", + .udesc = "NO QPI credits", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RTID", + .udesc = "No RTIDs", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_rxr_occupancy[]={ + { .uname = "IPQ", + .udesc = "IPQ", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ", + .udesc = "IRQ", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_REJECTED", + .udesc = "IRQ rejected", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VFIFO", + .udesc = "Number of used entries in the IRQ ordering FIFO in each cycle", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_c_tor_inserts[]={ + { .uname = "EVICTION", + .udesc = "Number of Evictions transactions inserted into TOR", + .ucode = 0x400, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "MISS_ALL", + .udesc = "Number of miss requests inserted into the TOR", + .ucode = 0xa00, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "MISS_OPCODE", + .udesc = "Number of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)", + .ucode = 0x300, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NID_ALL", + .udesc = "Number of NID-matched transactions inserted into the TOR", + .ucode = 0x4800, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "NID_EVICTION", + .udesc = "Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)", + .ucode = 0x4400, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "NID_MISS_ALL", + .udesc = "Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)", + .ucode = 0x4a00, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "NID_MISS_OPCODE", + .udesc = "Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)", + .ucode = 0x4300, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NID_OPCODE", + .udesc = "Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)", + .ucode = 0x4100, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NID_WB", + .udesc = "Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)", + .ucode = 0x5000, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "OPCODE", + .udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)", + .ucode = 0x100, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WB", + .udesc = "Number of write transactions inserted into the TOR", + .ucode = 0x1000, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + CBO_FILT_OPC(1) +}; + +static const intel_x86_umask_t snbep_unc_c_tor_occupancy[]={ + { .uname = "ALL", + .udesc = "All valid TOR entries", + .ucode = 0x800, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "EVICTION", + .udesc = "Number of outstanding eviction transactions in the TOR", + .ucode = 0x400, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "MISS_ALL", + .udesc = "Number of outstanding miss requests in the TOR", + .ucode = 0xa00, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "MISS_OPCODE", + .udesc = "Number of TOR entries that match a NID and an opcode (must provide opc_* umask)", + .ucode = 0x300, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NID_ALL", + .udesc = "Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)", + .ucode = 0x4800, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "NID_EVICTION", + .udesc = "Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)", + .ucode = 0x4400, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "NID_MISS_ALL", + .udesc = "Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)", + .ucode = 0x4a00, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "NID_MISS_OPCODE", + .udesc = "Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)", + .ucode = 0x4300, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NID_OPCODE", + .udesc = "Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)", + .ucode = 0x4100, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OPCODE", + .udesc = "Number of TOR entries that match an opcode (must provide opc_* umask)", + .ucode = 0x100, + .grpid = 0, + .uflags = INTEL_X86_NCOMBO, + }, + CBO_FILT_OPC(1) +}; + +static const intel_x86_umask_t snbep_unc_c_txr_inserts[]={ + { .uname = "AD_CACHE", + .udesc = "Counts the number of ring transactions from Cachebo to AD ring", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_CACHE", + .udesc = "Counts the number of ring transactions from Cachebo to AK ring", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CACHE", + .udesc = "Counts the number of ring transactions from Cachebo to BL ring", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_CACHE", + .udesc = "Counts the number of ring transactions from Cachebo ton IV ring", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CORE", + .udesc = "Counts the number of ring transactions from Corebo to AD ring", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_CORE", + .udesc = "Counts the number of ring transactions from Corebo to AK ring", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CORE", + .udesc = "Counts the number of ring transactions from Corebo to BL ring", + .ucode = 0x4000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_snbep_unc_c_pe[]={ + { .name = "UNC_C_CLOCKTICKS", + .desc = "C-box Uncore clockticks", + .modmsk = 0x0, + .cntmsk = 0xf, + .code = 0x00, + .flags = INTEL_X86_FIXED, + }, + { .name = "UNC_C_COUNTER0_OCCUPANCY", + .desc = "Counter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0xe, + .code = 0x1f, + }, + { .name = "UNC_C_ISMQ_DRD_MISS_OCC", + .desc = "TBD", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x21, + }, + { .name = "UNC_C_LLC_LOOKUP", + .desc = "Cache lookups. Counts number of times the LLC is accessed from L2 for code, data, prefetches (Must set filter mask bit 0 and select )", + .modmsk = SNBEP_UNC_CBO_NID_ATTRS, + .cntmsk = 0x3, + .code = 0x34, + .ngrp = 2, + .flags = INTEL_X86_NO_AUTOENCODE, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_llc_lookup), + .umasks = snbep_unc_c_llc_lookup, + }, + { .name = "UNC_C_LLC_VICTIMS", + .desc = "Lines victimized", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x37, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_llc_victims), + .ngrp = 1, + .umasks = snbep_unc_c_llc_victims, + }, + { .name = "UNC_C_MISC", + .desc = "Miscelleanous C-Box events", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x39, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_misc), + .ngrp = 1, + .umasks = snbep_unc_c_misc, + }, + { .name = "UNC_C_RING_AD_USED", + .desc = "Address ring in use. Counts number of cycles ring is being used at this ring stop", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0xc, + .code = 0x1b, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_ad_used), + .ngrp = 1, + .umasks = snbep_unc_c_ring_ad_used, + }, + { .name = "UNC_C_RING_AK_USED", + .desc = "Acknowledgement ring in use. Counts number of cycles ring is being used at this ring stop", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0xc, + .code = 0x1c, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ + .ngrp = 1, + .umasks = snbep_unc_c_ring_ad_used, + }, + { .name = "UNC_C_RING_BL_USED", + .desc = "Bus or Data ring in use. Counts number of cycles ring is being used at this ring stop", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0xc, + .code = 0x1d, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ + .ngrp = 1, + .umasks = snbep_unc_c_ring_ad_used, + }, + { .name = "UNC_C_RING_BOUNCES", + .desc = "Number of LLC responses that bounced in the ring", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x05, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_bounces), + .ngrp = 1, + .umasks = snbep_unc_c_ring_bounces, + }, + { .name = "UNC_C_RING_IV_USED", + .desc = "Invalidate ring in use. Counts number of cycles ring is being used at this ring stop", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0xc, + .code = 0x1e, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_ring_iv_used), + .ngrp = 1, + .umasks = snbep_unc_c_ring_iv_used, + }, + { .name = "UNC_C_RING_SRC_THRTL", + .desc = "TDB", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x07, + }, + { .name = "UNC_C_RXR_EXT_STARVED", + .desc = "Ingress arbiter blockig cycles", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x12, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_ext_starved), + .ngrp = 1, + .umasks = snbep_unc_c_rxr_ext_starved, + }, + { .name = "UNC_C_RXR_INSERTS", + .desc = "Ingress Allocations", + .code = 0x13, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_CBO_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_inserts), + .umasks = snbep_unc_c_rxr_inserts + }, + { .name = "UNC_C_RXR_IPQ_RETRY", + .desc = "Probe Queue Retries", + .code = 0x31, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_CBO_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_ipq_retry), + .umasks = snbep_unc_c_rxr_ipq_retry + }, + { .name = "UNC_C_RXR_IRQ_RETRY", + .desc = "Ingress Request Queue Rejects", + .code = 0x32, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_CBO_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_irq_retry), + .umasks = snbep_unc_c_rxr_irq_retry + }, + { .name = "UNC_C_RXR_ISMQ_RETRY", + .desc = "ISMQ Retries", + .code = 0x33, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_CBO_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_ismq_retry), + .umasks = snbep_unc_c_rxr_ismq_retry + }, + { .name = "UNC_C_RXR_OCCUPANCY", + .desc = "Ingress Occupancy", + .code = 0x11, + .cntmsk = 0x1, + .ngrp = 1, + .modmsk = SNBEP_UNC_CBO_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_rxr_inserts), + .umasks = snbep_unc_c_rxr_inserts, /* identical to snbep_unc_c_rxr_inserts */ + }, + { .name = "UNC_C_TOR_INSERTS", + .desc = "TOR Inserts", + .code = 0x35, + .cntmsk = 0x3, + .ngrp = 2, + .modmsk = SNBEP_UNC_CBO_NID_ATTRS, + .flags = INTEL_X86_NO_AUTOENCODE, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_tor_inserts), + .umasks = snbep_unc_c_tor_inserts + }, + { .name = "UNC_C_TOR_OCCUPANCY", + .desc = "TOR Occupancy", + .code = 0x36, + .cntmsk = 0x1, + .ngrp = 2, + .modmsk = SNBEP_UNC_CBO_NID_ATTRS, + .flags = INTEL_X86_NO_AUTOENCODE, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_tor_occupancy), + .umasks = snbep_unc_c_tor_occupancy + }, + { .name = "UNC_C_TXR_ADS_USED", + .desc = "Egress events", + .code = 0x04, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_CBO_ATTRS, + }, + { .name = "UNC_C_TXR_INSERTS", + .desc = "Egress allocations", + .code = 0x02, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_CBO_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_txr_inserts), + .umasks = snbep_unc_c_txr_inserts + }, +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_ha_events.h b/src/libpfm4/lib/events/intel_snbep_unc_ha_events.h new file mode 100644 index 0000000..68d4090 --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_ha_events.h @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * This file has been automatically generated. + * + * PMU: snbep_unc_ha (Intel SandyBridge-EP HA uncore PMU) + */ + +static const intel_x86_umask_t snbep_unc_h_conflict_cycles[]={ + { .uname = "CONFLICT", + .udesc = "Number of cycles that we are handling conflicts", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_CONFLICT", + .udesc = "Number of cycles that we are not handling conflicts", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_directory_lookup[]={ + { .uname = "NO_SNP", + .udesc = "Snoop not needed", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Snoop needed", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_directory_update[]={ + { .uname = "ANY", + .udesc = "Counts any directory update", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CLEAR", + .udesc = "Directory clears", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SET", + .udesc = "Directory set", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_igr_no_credit_cycles[]={ + { .uname = "AD_QPI0", + .udesc = "AD to QPI link 0", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_QPI1", + .udesc = "AD to QPI link 1", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_QPI0", + .udesc = "BL to QPI link 0", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_QPI1", + .udesc = "BL to QPI link 1", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_imc_writes[]={ + { .uname = "ALL", + .udesc = "Counts all writes", + .ucode = 0xf00, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "FULL", + .udesc = "Counts full line non ISOCH", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FULL_ISOCH", + .udesc = "Counts ISOCH full line", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARTIAL", + .udesc = "Counts partial non-ISOCH", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARTIAL_ISOCH", + .udesc = "Counts ISOCH partial", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_requests[]={ + { .uname = "READS", + .udesc = "Counts incoming read requests. Good proxy for LLC read misses, incl. RFOs", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITES", + .udesc = "Counts incoming writes", + .ucode = 0xc00, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_rpq_cycles_no_reg_credits[]={ + { .uname = "CHN0", + .udesc = "Channel 0", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN1", + .udesc = "Channel 1", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN2", + .udesc = "channel 2", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN3", + .udesc = "Chanell 3", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_tad_requests_g0[]={ + { .uname = "REGION0", + .udesc = "Counts for TAD Region 0", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION1", + .udesc = "Counts for TAD Region 1", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION2", + .udesc = "Counts for TAD Region 2", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION3", + .udesc = "Counts for TAD Region 3", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION4", + .udesc = "Counts for TAD Region 4", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION5", + .udesc = "Counts for TAD Region 5", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION6", + .udesc = "Counts for TAD Region 6", + .ucode = 0x4000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION7", + .udesc = "Counts for TAD Region 7", + .ucode = 0x8000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_tad_requests_g1[]={ + { .uname = "REGION8", + .udesc = "Counts for TAD Region 8", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION9", + .udesc = "Counts for TAD Region 9", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION10", + .udesc = "Counts for TAD Region 10", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REGION11", + .udesc = "Counts for TAD Region 11", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_tracker_inserts[]={ + { .uname = "ALL", + .udesc = "Counts all requests", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_txr_ad[]={ + { .uname = "NDR", + .udesc = "Counts non-data responses", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Counts outbound snoops send on the ring", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_txr_ad_cycles_full[]={ + { .uname = "ALL", + .udesc = "Counts cycles full from both schedulers", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "SCHED0", + .udesc = "Counts cycles full from scheduler bank 0", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SCHED1", + .udesc = "Counts cycles full from scheduler bank 1", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_txr_ak_cycles_full[]={ + { .uname = "ALL", + .udesc = "Counts cycles from both schedulers", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "SCHED0", + .udesc = "Counts cycles from scheduler bank 0", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SCHED1", + .udesc = "Counts cycles from scheduler bank 1", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_txr_bl[]={ + { .uname = "DRS_CACHE", + .udesc = "Counts data being sent to the cache", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_CORE", + .udesc = "Counts data being sent directly to the requesting core", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_QPI", + .udesc = "Counts data being sent to a remote socket over QPI", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_wpq_cycles_no_reg_credits[]={ + { .uname = "CHN0", + .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN1", + .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN2", + .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN3", + .udesc = "HA iMC CHN0 WPQ Credits Empty - Regular", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_h_txr_bl_cycles_full[]={ + { .uname = "ALL", + .udesc = "BL Egress Full", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SCHED0", + .udesc = "BL Egress Full", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SCHED1", + .udesc = "BL Egress Full", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +#if 0 +static const intel_x86_umask_t snbep_unc_h_addr_opc_match[]={ + { .uname = "FILT", + .udesc = "Number of addr and opcode matches (opc via opc= or address via addr= modifiers)", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_ADDR, + }, +}; +#endif + +static const intel_x86_entry_t intel_snbep_unc_h_pe[]={ + { .name = "UNC_H_CLOCKTICKS", + .desc = "HA Uncore clockticks", + .modmsk = SNBEP_UNC_HA_ATTRS, + .cntmsk = 0xf, + .code = 0x00, + }, + { .name = "UNC_H_CONFLICT_CYCLES", + .desc = "Conflict Checks", + .code = 0xb, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_conflict_cycles), + .umasks = snbep_unc_h_conflict_cycles, + }, + { .name = "UNC_H_DIRECT2CORE_COUNT", + .desc = "Direct2Core Messages Sent", + .code = 0x11, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_HA_ATTRS, + }, + { .name = "UNC_H_DIRECT2CORE_CYCLES_DISABLED", + .desc = "Cycles when Direct2Core was Disabled", + .code = 0x12, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_HA_ATTRS, + }, + { .name = "UNC_H_DIRECT2CORE_TXN_OVERRIDE", + .desc = "Number of Reads that had Direct2Core Overridden", + .code = 0x13, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_HA_ATTRS, + }, + { .name = "UNC_H_DIRECTORY_LOOKUP", + .desc = "Directory Lookups", + .code = 0xc, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_directory_lookup), + .umasks = snbep_unc_h_directory_lookup + }, + { .name = "UNC_H_DIRECTORY_UPDATE", + .desc = "Directory Updates", + .code = 0xd, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_directory_update), + .umasks = snbep_unc_h_directory_update + }, + { .name = "UNC_H_IGR_NO_CREDIT_CYCLES", + .desc = "Cycles without QPI Ingress Credits", + .code = 0x22, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_igr_no_credit_cycles), + .umasks = snbep_unc_h_igr_no_credit_cycles + }, + { .name = "UNC_H_IMC_RETRY", + .desc = "Retry Events", + .code = 0x1e, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_HA_ATTRS, + }, + { .name = "UNC_H_IMC_WRITES", + .desc = "HA to iMC Full Line Writes Issued", + .code = 0x1a, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_imc_writes), + .umasks = snbep_unc_h_imc_writes + }, + { .name = "UNC_H_REQUESTS", + .desc = "Read and Write Requests", + .code = 0x1, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_requests), + .umasks = snbep_unc_h_requests + }, + { .name = "UNC_H_RPQ_CYCLES_NO_REG_CREDITS", + .desc = "iMC RPQ Credits Empty - Regular", + .code = 0x15, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_rpq_cycles_no_reg_credits), + .umasks = snbep_unc_h_rpq_cycles_no_reg_credits + }, + { .name = "UNC_H_TAD_REQUESTS_G0", + .desc = "HA Requests to a TAD Region - Group 0", + .code = 0x1b, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_tad_requests_g0), + .umasks = snbep_unc_h_tad_requests_g0 + }, + { .name = "UNC_H_TAD_REQUESTS_G1", + .desc = "HA Requests to a TAD Region - Group 1", + .code = 0x1c, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_tad_requests_g1), + .umasks = snbep_unc_h_tad_requests_g1 + }, + { .name = "UNC_H_TRACKER_INSERTS", + .desc = "Tracker Allocations", + .code = 0x6, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_tracker_inserts), + .umasks = snbep_unc_h_tracker_inserts + }, + { .name = "UNC_H_TXR_AD", + .desc = "Outbound NDR Ring Transactions", + .code = 0xf, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ad), + .umasks = snbep_unc_h_txr_ad + }, + { .name = "UNC_H_TXR_AD_CYCLES_FULL", + .desc = "AD Egress Full", + .code = 0x2a, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ad_cycles_full), + .umasks = snbep_unc_h_txr_ad_cycles_full + }, + { .name = "UNC_H_TXR_AK_CYCLES_FULL", + .desc = "AK Egress Full", + .code = 0x32, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ak_cycles_full), + .umasks = snbep_unc_h_txr_ak_cycles_full + }, + { .name = "UNC_H_TXR_AK_NDR", + .desc = "Outbound NDR Ring Transactions", + .code = 0xe, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_HA_ATTRS, + }, + { .name = "UNC_H_TXR_BL", + .desc = "Outbound DRS Ring Transactions to Cache", + .code = 0x10, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_bl), + .umasks = snbep_unc_h_txr_bl + }, + { .name = "UNC_H_TXR_BL_CYCLES_FULL", + .desc = "BL Egress Full", + .code = 0x36, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_txr_ak_cycles_full), + .umasks = snbep_unc_h_txr_ak_cycles_full, /* identical to snbep_unc_h_txr_ak_cycles_full */ + }, + { .name = "UNC_H_WPQ_CYCLES_NO_REG_CREDITS", + .desc = "HA iMC CHN0 WPQ Credits Empty - Regular", + .code = 0x18, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_rpq_cycles_no_reg_credits), + .umasks = snbep_unc_h_rpq_cycles_no_reg_credits , /* identical to snbep_unc_h_rpq_cycles_no_reg_credits */ + }, +#if 0 + { .name = "UNC_H_ADDR_OPC_MATCH", + .desc = "QPI address/opcode match", + .code = 0x20, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_HA_OPC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_h_addr_opc_match), + .umasks = snbep_unc_h_addr_opc_match, + }, +#endif +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_imc_events.h b/src/libpfm4/lib/events/intel_snbep_unc_imc_events.h new file mode 100644 index 0000000..e2494b2 --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_imc_events.h @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: snbep_unc_imc (Intel SandyBridge-EP IMC uncore PMU) + */ + +static const intel_x86_umask_t snbep_unc_m_cas_count[]={ + { .uname = "ALL", + .udesc = "Counts total number of DRAM CAS commands issued on this channel", + .ucode = 0xf00, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "RD", + .udesc = "Counts all DRAM reads on this channel, incl. underfills", + .ucode = 0x300, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_REG", + .udesc = "Counts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit precharge", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_UNDERFILL", + .udesc = "Counts number of underfill reads issued by the memory controller", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "Counts number of DRAM write CAS commands on this channel", + .ucode = 0xc00, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR_RMM", + .udesc = "Counts Number of opportunistic DRAM write CAS commands issued on this channel", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR_WMM", + .udesc = "Counts number of DRAM write CAS commands issued on this channel while in Write-Major mode", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_m_dram_refresh[]={ + { .uname = "HIGH", + .udesc = "TBD", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PANIC", + .udesc = "TBD", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_m_major_modes[]={ + { .uname = "ISOCH", + .udesc = "Counts cycles in ISOCH Major maode", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARTIAL", + .udesc = "Counts cycles in Partial Major mode", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ", + .udesc = "Counts cycles in Read Major mode", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITE", + .udesc = "Counts cycles in Write Major mode", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_m_power_cke_cycles[]={ + { .uname = "RANK0", + .udesc = "Count cycles for rank 0", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RANK1", + .udesc = "Count cycles for rank 1", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RANK2", + .udesc = "Count cycles for rank 2", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RANK3", + .udesc = "Count cycles for rank 3", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RANK4", + .udesc = "Count cycles for rank 4", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RANK5", + .udesc = "Count cycles for rank 5", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RANK6", + .udesc = "Count cycles for rank 6", + .ucode = 0x4000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RANK7", + .udesc = "Count cycles for rank 7", + .ucode = 0x8000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_m_preemption[]={ + { .uname = "RD_PREEMPT_RD", + .udesc = "Counts read over read preemptions", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_PREEMPT_WR", + .udesc = "Counts read over write preemptions", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_m_pre_count[]={ + { .uname = "PAGE_CLOSE", + .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of the page close counter expiring", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PAGE_MISS", + .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of page misses", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_snbep_unc_m_pe[]={ + { .name = "UNC_M_CLOCKTICKS", + .desc = "IMC Uncore clockticks", + .modmsk = 0x0, + .cntmsk = 0x100000000ull, + .code = 0xff, /* perf pseudo encoding for fixed counter */ + .flags = INTEL_X86_FIXED, + }, + { .name = "UNC_M_ACT_COUNT", + .desc = "DRAM Activate Count", + .code = 0x1, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_CAS_COUNT", + .desc = "DRAM RD_CAS and WR_CAS Commands.", + .code = 0x4, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_IMC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_cas_count), + .umasks = snbep_unc_m_cas_count + }, + { .name = "UNC_M_DRAM_PRE_ALL", + .desc = "DRAM Precharge All Commands", + .code = 0x6, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_DRAM_REFRESH", + .desc = "Number of DRAM Refreshes Issued", + .code = 0x5, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_IMC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_dram_refresh), + .umasks = snbep_unc_m_dram_refresh + }, + { .name = "UNC_M_ECC_CORRECTABLE_ERRORS", + .desc = "ECC Correctable Errors", + .code = 0x9, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_MAJOR_MODES", + .desc = "Cycles in a Major Mode", + .code = 0x7, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_IMC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_major_modes), + .umasks = snbep_unc_m_major_modes + }, + { .name = "UNC_M_POWER_CHANNEL_DLLOFF", + .desc = "Channel DLLOFF Cycles", + .code = 0x84, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_POWER_CHANNEL_PPD", + .desc = "Channel PPD Cycles", + .code = 0x85, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_POWER_CKE_CYCLES", + .desc = "CKE_ON_CYCLES by Rank", + .code = 0x83, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_IMC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_power_cke_cycles), + .umasks = snbep_unc_m_power_cke_cycles + }, + { .name = "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", + .desc = "Critical Throttle Cycles", + .code = 0x86, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_POWER_SELF_REFRESH", + .desc = "Clock-Enabled Self-Refresh", + .code = 0x43, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_POWER_THROTTLE_CYCLES", + .desc = "Throttle Cycles for Rank 0", + .code = 0x41, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_IMC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_power_cke_cycles), + .umasks = snbep_unc_m_power_cke_cycles /* identical to snbep_unc_m_power_cke_cycles */ + }, + { .name = "UNC_M_PREEMPTION", + .desc = "Read Preemption Count", + .code = 0x8, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_IMC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_preemption), + .umasks = snbep_unc_m_preemption + }, + { .name = "UNC_M_PRE_COUNT", + .desc = "DRAM Precharge commands.", + .code = 0x2, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_IMC_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_m_pre_count), + .umasks = snbep_unc_m_pre_count + }, + { .name = "UNC_M_RPQ_CYCLES_FULL", + .desc = "Read Pending Queue Full Cycles", + .code = 0x12, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_RPQ_CYCLES_NE", + .desc = "Read Pending Queue Not Empty", + .code = 0x11, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_RPQ_INSERTS", + .desc = "Read Pending Queue Allocations", + .code = 0x10, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_RPQ_OCCUPANCY", + .desc = "Read Pending Queue Occupancy", + .code = 0x80, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_WPQ_CYCLES_FULL", + .desc = "Write Pending Queue Full Cycles", + .code = 0x22, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_WPQ_CYCLES_NE", + .desc = "Write Pending Queue Not Empty", + .code = 0x21, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_WPQ_INSERTS", + .desc = "Write Pending Queue Allocations", + .code = 0x20, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_WPQ_OCCUPANCY", + .desc = "Write Pending Queue Occupancy", + .code = 0x81, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_WPQ_READ_HIT", + .desc = "Write Pending Queue CAM Match", + .code = 0x23, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, + { .name = "UNC_M_WPQ_WRITE_HIT", + .desc = "Write Pending Queue CAM Match", + .code = 0x24, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_IMC_ATTRS, + }, +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_pcu_events.h b/src/libpfm4/lib/events/intel_snbep_unc_pcu_events.h new file mode 100644 index 0000000..dd4aa3e --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_pcu_events.h @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: snbep_unc_pcu (Intel SandyBridge-EP PCU uncore) + */ + +static const intel_x86_umask_t snbep_unc_p_power_state_occupancy[]={ + { .uname = "CORES_C0", + .udesc = "Counts number of cores in C0", + .ucode = 0x4000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CORES_C3", + .udesc = "Counts number of cores in C3", + .ucode = 0x8000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CORES_C6", + .udesc = "Counts number of cores in C6", + .ucode = 0xc000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_p_occupancy_counters[]={ + { .uname = "C0", + .udesc = "Counts number of cores in C0", + .ucode = 0x0100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "C3", + .udesc = "Counts number of cores in C3", + .ucode = 0x0200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "C6", + .udesc = "Counts number of cores in C6", + .ucode = 0x0300, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_snbep_unc_p_pe[]={ + { .name = "UNC_P_CLOCKTICKS", + .desc = "PCU Uncore clockticks", + .modmsk = SNBEP_UNC_PCU_ATTRS, + .cntmsk = 0xf, + .code = 0x00, + }, + { .name = "UNC_P_CORE0_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0x3 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_CORE1_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0x4 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_CORE2_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0x5 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_CORE3_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0x6 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_CORE4_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0x7 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_CORE5_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0x8 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_CORE6_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0x9 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_CORE7_TRANSITION_CYCLES", + .desc = "Core C State Transition Cycles", + .code = 0xa | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_DEMOTIONS_CORE0", + .desc = "Core C State Demotions", + .code = 0x1e, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_DEMOTIONS_CORE1", + .desc = "Core C State Demotions", + .code = 0x1f, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_DEMOTIONS_CORE2", + .desc = "Core C State Demotions", + .code = 0x20, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_DEMOTIONS_CORE3", + .desc = "Core C State Demotions", + .code = 0x21, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_DEMOTIONS_CORE4", + .desc = "Core C State Demotions", + .code = 0x22, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_DEMOTIONS_CORE5", + .desc = "Core C State Demotions", + .code = 0x23, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_DEMOTIONS_CORE6", + .desc = "Core C State Demotions", + .code = 0x24, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_DEMOTIONS_CORE7", + .desc = "Core C State Demotions", + .code = 0x25, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_FREQ_BAND0_CYCLES", + .desc = "Frequency Residency", + .code = 0xb, + .cntmsk = 0xf, + .flags = INTEL_X86_NO_AUTOENCODE, + .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, + .modmsk_req = _SNBEP_UNC_ATTR_FF, + }, + { .name = "UNC_P_FREQ_BAND1_CYCLES", + .desc = "Frequency Residency", + .code = 0xc, + .cntmsk = 0xf, + .flags = INTEL_X86_NO_AUTOENCODE, + .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, + .modmsk_req = _SNBEP_UNC_ATTR_FF, + }, + { .name = "UNC_P_FREQ_BAND2_CYCLES", + .desc = "Frequency Residency", + .code = 0xd, + .cntmsk = 0xf, + .flags = INTEL_X86_NO_AUTOENCODE, + .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, + .modmsk_req = _SNBEP_UNC_ATTR_FF, + }, + { .name = "UNC_P_FREQ_BAND3_CYCLES", + .desc = "Frequency Residency", + .code = 0xe, + .cntmsk = 0xf, + .flags = INTEL_X86_NO_AUTOENCODE, + .modmsk = SNBEP_UNC_PCU_BAND_ATTRS, + .modmsk_req = _SNBEP_UNC_ATTR_FF, + }, + { .name = "UNC_P_FREQ_MAX_CURRENT_CYCLES", + .desc = "Current Strongest Upper Limit Cycles", + .code = 0x7, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + .desc = "Thermal Strongest Upper Limit Cycles", + .code = 0x4, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_FREQ_MAX_OS_CYCLES", + .desc = "OS Strongest Upper Limit Cycles", + .code = 0x6, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_FREQ_MAX_POWER_CYCLES", + .desc = "Power Strongest Upper Limit Cycles", + .code = 0x5, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES", + .desc = "IO P Limit Strongest Lower Limit Cycles", + .code = 0x1 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_FREQ_MIN_PERF_P_CYCLES", + .desc = "Perf P Limit Strongest Lower Limit Cycles", + .code = 0x2 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_FREQ_TRANS_CYCLES", + .desc = "Cycles spent changing Frequency", + .code = 0x0 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_occupancy_counters), + .umasks = snbep_unc_p_occupancy_counters + }, + { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + .desc = "Memory Phase Shedding Cycles", + .code = 0x2f, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_POWER_STATE_OCCUPANCY", + .desc = "Number of cores in C0", + .code = 0x80, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_PCU_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_p_power_state_occupancy), + .umasks = snbep_unc_p_power_state_occupancy + }, + { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES", + .desc = "External Prochot", + .code = 0xa, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES", + .desc = "Internal Prochot", + .code = 0x9, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_TOTAL_TRANSITION_CYCLES", + .desc = "Total Core C State Transition Cycles", + .code = 0xb | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_VOLT_TRANS_CYCLES_CHANGE", + .desc = "Cycles Changing Voltage", + .code = 0x3, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_VOLT_TRANS_CYCLES_DECREASE", + .desc = "Cycles Decreasing Voltage", + .code = 0x2, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_VOLT_TRANS_CYCLES_INCREASE", + .desc = "Cycles Increasing Voltage", + .code = 0x1, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, + { .name = "UNC_P_VR_HOT_CYCLES", + .desc = "VR Hot", + .code = 0x32, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_PCU_ATTRS, + }, +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_qpi_events.h b/src/libpfm4/lib/events/intel_snbep_unc_qpi_events.h new file mode 100644 index 0000000..0925918 --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_qpi_events.h @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * This file has been automatically generated. + * + * PMU: snbep_unc_qpi (Intel SandyBridge-EP QPI uncore) + */ + +static const intel_x86_umask_t snbep_unc_q_direct2core[]={ + { .uname = "FAILURE_CREDITS", + .udesc = "Number of spawn failures due to lack of Egress credits", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FAILURE_CREDITS_RBT", + .udesc = "Number of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not set", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FAILURE_RBT", + .udesc = "Number of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transaction", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SUCCESS", + .udesc = "Number of spawn successes", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_q_rxl_credits_consumed_vn0[]={ + { .uname = "DRS", + .udesc = "Number of times VN0 consumed for DRS message class", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HOM", + .udesc = "Number of times VN0 consumed for HOM message class", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB", + .udesc = "Number of times VN0 consumed for NCB message class", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "Number of times VN0 consumed for NCS message class", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NDR", + .udesc = "Number of times VN0 consumed for NDR message class", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Number of times VN0 consumed for SNP message class", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_q_rxl_flits_g0[]={ + { .uname = "DATA", + .udesc = "Number of data flits over QPI", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IDLE", + .udesc = "Number of flits over QPI that do not hold protocol payload", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NON_DATA", + .udesc = "Number of non-NULL non-data flits over QPI", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_q_rxl_flits_g1[]={ + { .uname = "DRS", + .udesc = "Number of flits over QPI on the Data Response (DRS) channel", + .ucode = 0x1800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_DATA", + .udesc = "Number of data flits over QPI on the Data Response (DRS) channel", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_NONDATA", + .udesc = "Number of protocol flits over QPI on the Data Response (DRS) channel", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HOM", + .udesc = "Number of flits over QPI on the home channel", + .ucode = 0x600, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HOM_NONREQ", + .udesc = "Number of non-request flits over QPI on the home channel", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HOM_REQ", + .udesc = "Number of data requests over QPI on the home channel", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Number of snoop requests flits over QPI", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_q_rxl_flits_g2[]={ + { .uname = "NCB", + .udesc = "Number of non-coherent bypass flits", + .ucode = 0xc00, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB_DATA", + .udesc = "Number of non-coherent data flits", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB_NONDATA", + .udesc = "Number of bypass non-data flits", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "Number of non-coherent standard (NCS) flits", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NDR_AD", + .udesc = "Number of flits received over Non-data response (NDR) channel", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NDR_AK", + .udesc = "Number of flits received on the Non-data response (NDR) channel)", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_snbep_unc_q_pe[]={ + { .name = "UNC_Q_CLOCKTICKS", + .desc = "Number of qfclks", + .code = 0x14, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_CTO_COUNT", + .desc = "Count of CTO Events", + .code = 0x38, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_DIRECT2CORE", + .desc = "Direct 2 Core Spawning", + .code = 0x13, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_direct2core), + .umasks = snbep_unc_q_direct2core + }, + { .name = "UNC_Q_L1_POWER_CYCLES", + .desc = "Cycles in L1", + .code = 0x12, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL0P_POWER_CYCLES", + .desc = "Cycles in L0p", + .code = 0x10, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL0_POWER_CYCLES", + .desc = "Cycles in L0", + .code = 0xf, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_BYPASSED", + .desc = "Rx Flit Buffer Bypassed", + .code = 0x9, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN0", + .desc = "VN0 Credit Consumed", + .code = 0x1e | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_credits_consumed_vn0), + .umasks = snbep_unc_q_rxl_credits_consumed_vn0 + }, + { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VNA", + .desc = "VNA Credit Consumed", + .code = 0x1d | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_CYCLES_NE", + .desc = "RxQ Cycles Not Empty", + .code = 0xa, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_FLITS_G0", + .desc = "Flits Received - Group 0", + .code = 0x1, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g0), + .umasks = snbep_unc_q_rxl_flits_g0 + }, + { .name = "UNC_Q_RXL_FLITS_G1", + .desc = "Flits Received - Group 1", + .code = 0x2 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g1), + .umasks = snbep_unc_q_rxl_flits_g1 + }, + + { .name = "UNC_Q_RXL_FLITS_G2", + .desc = "Flits Received - Group 2", + .code = 0x3 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g2), + .umasks = snbep_unc_q_rxl_flits_g2 + }, + { .name = "UNC_Q_RXL_INSERTS", + .desc = "Rx Flit Buffer Allocations", + .code = 0x8, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_INSERTS_DRS", + .desc = "Rx Flit Buffer Allocations - DRS", + .code = 0x9 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_INSERTS_HOM", + .desc = "Rx Flit Buffer Allocations - HOM", + .code = 0xc | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_INSERTS_NCB", + .desc = "Rx Flit Buffer Allocations - NCB", + .code = 0xa | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_INSERTS_NCS", + .desc = "Rx Flit Buffer Allocations - NCS", + .code = 0xb | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_INSERTS_NDR", + .desc = "Rx Flit Buffer Allocations - NDR", + .code = 0xe | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_INSERTS_SNP", + .desc = "Rx Flit Buffer Allocations - SNP", + .code = 0xd | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_OCCUPANCY", + .desc = "RxQ Occupancy - All Packets", + .code = 0xb, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_OCCUPANCY_DRS", + .desc = "RxQ Occupancy - DRS", + .code = 0x15 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_OCCUPANCY_HOM", + .desc = "RxQ Occupancy - HOM", + .code = 0x18 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_OCCUPANCY_NCB", + .desc = "RxQ Occupancy - NCB", + .code = 0x16 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_OCCUPANCY_NCS", + .desc = "RxQ Occupancy - NCS", + .code = 0x17 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_OCCUPANCY_NDR", + .desc = "RxQ Occupancy - NDR", + .code = 0x1a | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_RXL_OCCUPANCY_SNP", + .desc = "RxQ Occupancy - SNP", + .code = 0x19 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_TXL0P_POWER_CYCLES", + .desc = "Cycles in L0p", + .code = 0xd, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_TXL0_POWER_CYCLES", + .desc = "Cycles in L0", + .code = 0xc, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_TXL_BYPASSED", + .desc = "Tx Flit Buffer Bypassed", + .code = 0x5, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_TXL_CYCLES_NE", + .desc = "Tx Flit Buffer Cycles not Empty", + .code = 0x6, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_TXL_FLITS_G0", + .desc = "Flits Transferred - Group 0", + .code = 0x0, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g0), + .umasks = snbep_unc_q_rxl_flits_g0 /* shared with rxl_flits_g0 */ + }, + { .name = "UNC_Q_TXL_FLITS_G1", + .desc = "Flits Transferred - Group 1", + .code = 0x0 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g1), + .umasks = snbep_unc_q_rxl_flits_g1 /* shared with rxl_flits_g1 */ + }, + { .name = "UNC_Q_TXL_FLITS_G2", + .desc = "Flits Transferred - Group 2", + .code = 0x1 | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_q_rxl_flits_g2), + .umasks = snbep_unc_q_rxl_flits_g2 /* shared with rxl_flits_g2 */ + }, + { .name = "UNC_Q_TXL_INSERTS", + .desc = "Tx Flit Buffer Allocations", + .code = 0x4, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_TXL_OCCUPANCY", + .desc = "Tx Flit Buffer Occupancy", + .code = 0x7, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_VNA_CREDIT_RETURNS", + .desc = "VNA Credits Returned", + .code = 0x1c | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, + { .name = "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + .desc = "VNA Credits Pending Return - Occupancy", + .code = 0x1b | (1ULL << 21), /* sel_ext */ + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_QPI_ATTRS, + }, +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_r2pcie_events.h b/src/libpfm4/lib/events/intel_snbep_unc_r2pcie_events.h new file mode 100644 index 0000000..2a5af45 --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_r2pcie_events.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * This file has been automatically generated. + * + * PMU: snbep_unc_r2pcie (Intel SandyBridge-EP R2PCIe uncore) + */ + +static const intel_x86_umask_t snbep_unc_r2_ring_ad_used[]={ + { .uname = "CCW_EVEN", + .udesc = "Counter-clockwise and even ring polarity", + .ucode = 0x400, + }, + { .uname = "CCW_ODD", + .udesc = "Counter-clockwise and odd ring polarity", + .ucode = 0x800, + }, + { .uname = "CW_EVEN", + .udesc = "Clockwise and even ring polarity", + .ucode = 0x100, + }, + { .uname = "CW_ODD", + .udesc = "Clockwise and odd ring polarity", + .ucode = 0x200, + }, + { .uname = "CW_ANY", + .udesc = "Clockwise with any polarity", + .ucode = 0x300, + }, + { .uname = "CCW_ANY", + .udesc = "Counter-clockwise with any polarity", + .ucode = 0xc00, + }, + { .uname = "ANY", + .udesc = "any direction and any polarity", + .ucode = 0xf00, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snbep_unc_r2_ring_iv_used[]={ + { .uname = "ANY", + .udesc = "R2 IV Ring in Use", + .ucode = 0xf00, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snbep_unc_r2_rxr_cycles_ne[]={ + { .uname = "DRS", + .udesc = "DRS Ingress queue", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB", + .udesc = "NCB Ingress queue", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "NCS Ingress queue", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_r2_txr_cycles_full[]={ + { .uname = "AD", + .udesc = "AD Egress queue", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK Egress queue", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL Egress queue", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_snbep_unc_r2_pe[]={ + { .name = "UNC_R2_CLOCKTICKS", + .desc = "Number of uclks in domain", + .code = 0x1, + .cntmsk = 0xf, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + }, + { .name = "UNC_R2_RING_AD_USED", + .desc = "R2 AD Ring in Use", + .code = 0x7, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_ad_used), + .umasks = snbep_unc_r2_ring_ad_used + }, + { .name = "UNC_R2_RING_AK_USED", + .desc = "R2 AK Ring in Use", + .code = 0x8, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_ad_used), + .umasks = snbep_unc_r2_ring_ad_used /* shared */ + }, + { .name = "UNC_R2_RING_BL_USED", + .desc = "R2 BL Ring in Use", + .code = 0x9, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_ad_used), + .umasks = snbep_unc_r2_ring_ad_used /* shared */ + }, + { .name = "UNC_R2_RING_IV_USED", + .desc = "R2 IV Ring in Use", + .code = 0xa, + .cntmsk = 0xf, + .ngrp = 1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_ring_iv_used), + .umasks = snbep_unc_r2_ring_iv_used + }, + { .name = "UNC_R2_RXR_AK_BOUNCES", + .desc = "AK Ingress Bounced", + .code = 0x12, + .cntmsk = 0x1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + }, + { .name = "UNC_R2_RXR_CYCLES_NE", + .desc = "Ingress Cycles Not Empty", + .code = 0x10, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_rxr_cycles_ne), + .umasks = snbep_unc_r2_rxr_cycles_ne + }, + { .name = "UNC_R2_TXR_CYCLES_FULL", + .desc = "Egress Cycles Full", + .code = 0x25, + .cntmsk = 0x1, + .ngrp = 1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_txr_cycles_full), + .umasks = snbep_unc_r2_txr_cycles_full + }, + { .name = "UNC_R2_TXR_CYCLES_NE", + .desc = "Egress Cycles Not Empty", + .code = 0x23, + .cntmsk = 0x1, + .ngrp = 1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r2_txr_cycles_full), + .umasks = snbep_unc_r2_txr_cycles_full /* shared */ + }, + { .name = "UNC_R2_TXR_INSERTS", + .desc = "Egress allocations", + .code = 0x24, + .cntmsk = 0x1, + .modmsk = SNBEP_UNC_R2PCIE_ATTRS, + }, +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_r3qpi_events.h b/src/libpfm4/lib/events/intel_snbep_unc_r3qpi_events.h new file mode 100644 index 0000000..5756a0b --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_r3qpi_events.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * This file has been automatically generated. + * + * PMU: snbep_unc_r3qpi (Intel SandyBridge-EP R3QPI uncore) + */ + +static const intel_x86_umask_t snbep_unc_r3_iio_credits_acquired[]={ + { .uname = "DRS", + .udesc = "DRS", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB", + .udesc = "NCB", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "NCS", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_r3_ring_ad_used[]={ + { .uname = "CCW_EVEN", + .udesc = "Counter-Clockwise and even ring polarity", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CCW_ODD", + .udesc = "Counter-Clockwise and odd ring polarity", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CW_EVEN", + .udesc = "Clockwise and even ring polarity", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CW_ODD", + .udesc = "Clockwise and odd ring polarity", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_r3_ring_iv_used[]={ + { .uname = "ANY", + .udesc = "Any polarity", + .ucode = 0xf00, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snbep_unc_r3_rxr_bypassed[]={ + { .uname = "AD", + .udesc = "Ingress Bypassed", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t snbep_unc_r3_rxr_cycles_ne[]={ + { .uname = "DRS", + .udesc = "DRS Ingress queue", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HOM", + .udesc = "HOM Ingress queue", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB", + .udesc = "NCB Ingress queue", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "NCS Ingress queue", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NDR", + .udesc = "NDR Ingress queue", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "SNP Ingress queue", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t snbep_unc_r3_vn0_credits_reject[]={ + { .uname = "DRS", + .udesc = "Filter DRS message class", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HOM", + .udesc = "Filter HOM message class", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB", + .udesc = "Filter NCB message class", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "Filter NCS message class", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NDR", + .udesc = "Filter NDR message class", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Filter SNP message class", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, +}; + + +static const intel_x86_entry_t intel_snbep_unc_r3_pe[]={ + { .name = "UNC_R3_CLOCKTICKS", + .desc = "Number of uclks in domain", + .code = 0x1, + .cntmsk = 0x7, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + }, + { .name = "UNC_R3_IIO_CREDITS_ACQUIRED", + .desc = "to IIO BL Credit Acquired", + .code = 0x20, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_iio_credits_acquired), + .umasks = snbep_unc_r3_iio_credits_acquired + }, + { .name = "UNC_R3_IIO_CREDITS_REJECT", + .desc = "to IIO BL Credit Rejected", + .code = 0x21, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_iio_credits_acquired), + .umasks = snbep_unc_r3_iio_credits_acquired /* shared */ + }, + { .name = "UNC_R3_IIO_CREDITS_USED", + .desc = "to IIO BL Credit In Use", + .code = 0x22, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_iio_credits_acquired), + .umasks = snbep_unc_r3_iio_credits_acquired /* shared */ + }, + { .name = "UNC_R3_RING_AD_USED", + .desc = "R3 AD Ring in Use", + .code = 0x7, + .cntmsk = 0x7, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_ad_used), + .umasks = snbep_unc_r3_ring_ad_used + }, + { .name = "UNC_R3_RING_AK_USED", + .desc = "R3 AK Ring in Use", + .code = 0x8, + .cntmsk = 0x7, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_ad_used), + .umasks = snbep_unc_r3_ring_ad_used /* shared */ + }, + { .name = "UNC_R3_RING_BL_USED", + .desc = "R3 BL Ring in Use", + .code = 0x9, + .cntmsk = 0x7, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_ad_used), + .umasks = snbep_unc_r3_ring_ad_used /* shared */ + }, + { .name = "UNC_R3_RING_IV_USED", + .desc = "R3 IV Ring in Use", + .code = 0xa, + .cntmsk = 0x7, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_ring_iv_used), + .umasks = snbep_unc_r3_ring_iv_used + }, + { .name = "UNC_R3_RXR_BYPASSED", + .desc = "Ingress Bypassed", + .code = 0x12, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_bypassed), + .umasks = snbep_unc_r3_rxr_bypassed + }, + { .name = "UNC_R3_RXR_CYCLES_NE", + .desc = "Ingress Cycles Not Empty", + .code = 0x10, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_cycles_ne), + .umasks = snbep_unc_r3_rxr_cycles_ne + }, + { .name = "UNC_R3_RXR_INSERTS", + .desc = "Ingress Allocations", + .code = 0x11, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_cycles_ne), + .umasks = snbep_unc_r3_rxr_cycles_ne /* shared */ + }, + { .name = "UNC_R3_RXR_OCCUPANCY", + .desc = "Ingress Occupancy Accumulator", + .code = 0x13, + .cntmsk = 0x1, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_rxr_cycles_ne), + .umasks = snbep_unc_r3_rxr_cycles_ne /* shared */ + }, + { .name = "UNC_R3_TXR_CYCLES_FULL", + .desc = "Egress cycles full", + .code = 0x25, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + }, + { .name = "UNC_R3_TXR_INSERTS", + .desc = "Egress allocations", + .code = 0x24, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + }, + { .name = "UNC_R3_TXR_NACK", + .desc = "Egress Nack", + .code = 0x26, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + }, + { .name = "UNC_R3_VN0_CREDITS_REJECT", + .desc = "VN0 Credit Acquisition Failed on DRS", + .code = 0x37, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_vn0_credits_reject), + .umasks = snbep_unc_r3_vn0_credits_reject + }, + { .name = "UNC_R3_VN0_CREDITS_USED", + .desc = "VN0 Credit Used", + .code = 0x36, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_vn0_credits_reject), + .umasks = snbep_unc_r3_vn0_credits_reject /* shared */ + }, + { .name = "UNC_R3_VNA_CREDITS_ACQUIRED", + .desc = "VNA credit Acquisitions", + .code = 0x33, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + }, + { .name = "UNC_R3_VNA_CREDITS_REJECT", + .desc = "VNA Credit Reject", + .code = 0x34, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_r3_vn0_credits_reject), + .umasks = snbep_unc_r3_vn0_credits_reject /* shared */ + }, + { .name = "UNC_R3_VNA_CREDIT_CYCLES_OUT", + .desc = "Cycles with no VNA credits available", + .code = 0x31, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + }, + { .name = "UNC_R3_VNA_CREDIT_CYCLES_USED", + .desc = "Cycles with 1 or more VNA credits in use", + .code = 0x32, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_R3QPI_ATTRS, + }, +}; diff --git a/src/libpfm4/lib/events/intel_snbep_unc_ubo_events.h b/src/libpfm4/lib/events/intel_snbep_unc_ubo_events.h new file mode 100644 index 0000000..730af28 --- /dev/null +++ b/src/libpfm4/lib/events/intel_snbep_unc_ubo_events.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: snbep_unc_ubo (Intel SandyBridge-EP U-Box uncore PMU) + */ + +static const intel_x86_umask_t snbep_unc_u_event_msg[]={ + { .uname = "DOORBELL_RCVD", + .udesc = "TBD", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "INT_PRIO", + .udesc = "TBD", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IPI_RCVD", + .udesc = "TBD", + .ucode = 0x400, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSI_RCVD", + .udesc = "TBD", + .ucode = 0x200, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VLW_RCVD", + .udesc = "TBD", + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_snbep_unc_u_pe[]={ + { .name = "UNC_U_EVENT_MSG", + .desc = "VLW Received", + .code = 0x42, + .cntmsk = 0x3, + .ngrp = 1, + .modmsk = SNBEP_UNC_UBO_ATTRS, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_u_event_msg), + .umasks = snbep_unc_u_event_msg + }, + { .name = "UNC_U_LOCK_CYCLES", + .desc = "IDI Lock/SplitLock Cycles", + .code = 0x44, + .cntmsk = 0x3, + .modmsk = SNBEP_UNC_UBO_ATTRS, + }, +}; diff --git a/src/libpfm4/lib/pfmlib_arm.c b/src/libpfm4/lib/pfmlib_arm.c index 40194be..fdd885e 100644 --- a/src/libpfm4/lib/pfmlib_arm.c +++ b/src/libpfm4/lib/pfmlib_arm.c @@ -33,6 +33,13 @@ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_arm_priv.h" +const pfmlib_attr_desc_t arm_mods[]={ + PFM_ATTR_B("k", "monitor at kernel level"), + PFM_ATTR_B("u", "monitor at user level"), + PFM_ATTR_B("hv", "monitor in hypervisor"), + PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ +}; + pfm_arm_config_t pfm_arm_cfg; #ifdef CONFIG_PFMLIB_OS_LINUX @@ -159,10 +166,37 @@ pfmlib_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) } #endif +static int +arm_num_mods(void *this, int idx) +{ + const arm_entry_t *pe = this_pe(this); + unsigned int mask; + + mask = pe[idx].modmsk; + return pfmlib_popcnt(mask); +} + +static inline int +arm_attr2mod(void *this, int pidx, int attr_idx) +{ + const arm_entry_t *pe = this_pe(this); + size_t x; + int n; + + n = attr_idx; + + pfmlib_for_each_bit(x, pe[pidx].modmsk) { + if (n == 0) + break; + n--; + } + return x; +} + static void -pfm_arm_display_reg(pfm_arm_reg_t reg, char *fstr) +pfm_arm_display_reg(void *this, pfmlib_event_desc_t *e, pfm_arm_reg_t reg) { - __pfm_vbprintf("[0x%x] %s\n", reg.val, fstr); + __pfm_vbprintf("[0x%x] %s\n", reg.val, e->fstr); } int @@ -199,16 +233,80 @@ pfm_arm_get_encoding(void *this, pfmlib_event_desc_t *e) { const arm_entry_t *pe = this_pe(this); + pfm_event_attr_info_t *a; pfm_arm_reg_t reg; + unsigned int plm = 0; + int i, idx, has_plm = 0; reg.val = pe[e->event].code; + + for (i = 0; i < e->nattrs; i++) { + a = attr(e, i); + + if (a->ctrl != PFM_ATTR_CTRL_PMU) + continue; + + if (a->type > PFM_ATTR_UMASK) { + uint64_t ival = e->attrs[i].ival; + + switch(a->idx) { + case ARM_ATTR_U: /* USR */ + if (ival) + plm |= PFM_PLM3; + has_plm = 1; + break; + case ARM_ATTR_K: /* OS */ + if (ival) + plm |= PFM_PLM0; + has_plm = 1; + break; + case ARM_ATTR_HV: /* HYPERVISOR */ + if (ival) + plm |= PFM_PLMH; + has_plm = 1; + break; + default: + return PFM_ERR_ATTR; + } + } + } + + if (arm_has_plm(this, e)) { + if (!has_plm) + plm = e->dfl_plm; + reg.evtsel.excl_pl1 = !(plm & PFM_PLM0); + reg.evtsel.excl_usr = !(plm & PFM_PLM3); + reg.evtsel.excl_hyp = !(plm & PFM_PLMH); + } + + evt_strcat(e->fstr, "%s", pe[e->event].name); + e->codes[0] = reg.val; e->count = 1; - evt_strcat(e->fstr, "%s", pe[e->event].name); + for (i = 0; i < e->npattrs; i++) { + if (e->pattrs[i].ctrl != PFM_ATTR_CTRL_PMU) + continue; - pfm_arm_display_reg(reg, e->fstr); + if (e->pattrs[i].type == PFM_ATTR_UMASK) + continue; + + idx = e->pattrs[i].idx; + switch(idx) { + case ARM_ATTR_K: + evt_strcat(e->fstr, ":%s=%lu", arm_mods[idx].name, !reg.evtsel.excl_pl1); + break; + case ARM_ATTR_U: + evt_strcat(e->fstr, ":%s=%lu", arm_mods[idx].name, !reg.evtsel.excl_usr); + break; + case ARM_ATTR_HV: + evt_strcat(e->fstr, ":%s=%lu", arm_mods[idx].name, !reg.evtsel.excl_hyp); + break; + } + } + + pfm_arm_display_reg(this, e, reg); return PFM_SUCCESS; } @@ -262,13 +360,29 @@ pfm_arm_validate_table(void *this, FILE *fp) int pfm_arm_get_event_attr_info(void *this, int pidx, int attr_idx, pfm_event_attr_info_t *info) { - return PFM_ERR_INVAL; + int idx; + + idx = arm_attr2mod(this, pidx, attr_idx); + info->name = arm_mods[idx].name; + info->desc = arm_mods[idx].desc; + info->type = arm_mods[idx].type; + info->code = idx; + + info->is_dfl = 0; + info->equiv = NULL; + info->ctrl = PFM_ATTR_CTRL_PMU; + info->idx = idx; /* namespace specific index */ + + info->dfl_val64 = 0; + info->is_precise = 0; + + return PFM_SUCCESS; } unsigned int pfm_arm_get_event_nattrs(void *this, int pidx) { - return 0; + return arm_num_mods(this, pidx); } int diff --git a/src/libpfm4/lib/pfmlib_arm_armv7_pmuv1.c b/src/libpfm4/lib/pfmlib_arm_armv7_pmuv1.c index 97b1845..943101a 100644 --- a/src/libpfm4/lib/pfmlib_arm_armv7_pmuv1.c +++ b/src/libpfm4/lib/pfmlib_arm_armv7_pmuv1.c @@ -35,6 +35,7 @@ #include "events/arm_cortex_a8_events.h" /* event tables */ #include "events/arm_cortex_a9_events.h" +#include "events/arm_cortex_a15_events.h" static int pfm_arm_detect_cortex_a8(void *this) @@ -42,15 +43,15 @@ pfm_arm_detect_cortex_a8(void *this) int ret; - ret = pfm_arm_detect(this); - if (ret != PFM_SUCCESS) + ret = pfm_arm_detect(this); + if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; - - if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ - (pfm_arm_cfg.part == 0xc08)) { /* Cortex-A8 */ - return PFM_SUCCESS; + + if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ + (pfm_arm_cfg.part == 0xc08)) { /* Cortex-A8 */ + return PFM_SUCCESS; } - return PFM_ERR_NOTSUPP; + return PFM_ERR_NOTSUPP; } static int @@ -59,15 +60,32 @@ pfm_arm_detect_cortex_a9(void *this) int ret; - ret = pfm_arm_detect(this); - if (ret != PFM_SUCCESS) + ret = pfm_arm_detect(this); + if (ret != PFM_SUCCESS) + return PFM_ERR_NOTSUPP; + + if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ + (pfm_arm_cfg.part==0xc09)) { /* Cortex-A8 */ + return PFM_SUCCESS; + } + return PFM_ERR_NOTSUPP; +} + +static int +pfm_arm_detect_cortex_a15(void *this) +{ + + int ret; + + ret = pfm_arm_detect(this); + if (ret != PFM_SUCCESS) return PFM_ERR_NOTSUPP; - - if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ - (pfm_arm_cfg.part==0xc09)) { /* Cortex-A8 */ - return PFM_SUCCESS; + + if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ + (pfm_arm_cfg.part==0xc0f)) { /* Cortex-A15 */ + return PFM_SUCCESS; } - return PFM_ERR_NOTSUPP; + return PFM_ERR_NOTSUPP; } /* Cortex A8 support */ @@ -119,3 +137,29 @@ pfmlib_pmu_t arm_cortex_a9_support={ PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), .get_event_nattrs = pfm_arm_get_event_nattrs, }; + +/* Cortex A15 support */ +pfmlib_pmu_t arm_cortex_a15_support={ + .desc = "ARM Cortex A15", + .name = "arm_ac15", + .pmu = PFM_PMU_ARM_CORTEX_A15, + .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a15_pe), + .type = PFM_PMU_TYPE_CORE, + .pe = arm_cortex_a15_pe, + + .pmu_detect = pfm_arm_detect_cortex_a15, + .max_encoding = 1, + .num_cntrs = 6, + .supported_plm = ARMV7_A15_PLM, + + .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, + PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), + .get_event_first = pfm_arm_get_event_first, + .get_event_next = pfm_arm_get_event_next, + .event_is_valid = pfm_arm_event_is_valid, + .validate_table = pfm_arm_validate_table, + .get_event_info = pfm_arm_get_event_info, + .get_event_attr_info = pfm_arm_get_event_attr_info, + PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), + .get_event_nattrs = pfm_arm_get_event_nattrs, +}; diff --git a/src/libpfm4/lib/pfmlib_arm_perf_event.c b/src/libpfm4/lib/pfmlib_arm_perf_event.c index 5ccfcd6..c19df5f 100644 --- a/src/libpfm4/lib/pfmlib_arm_perf_event.c +++ b/src/libpfm4/lib/pfmlib_arm_perf_event.c @@ -71,14 +71,17 @@ pfm_arm_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) continue; /* - * with perf_events, u and k are handled at the OS level - * via attr.exclude_* fields + * with perf_events, u and k, hv are handled at the OS + * level via attr.exclude_* fields */ + if (arm_has_plm(this, e) && e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { + if ( e->pattrs[i].idx == ARM_ATTR_U + || e->pattrs[i].idx == ARM_ATTR_K + || e->pattrs[i].idx == ARM_ATTR_HV) + compact = 1; + } if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { - if ( e->pattrs[i].idx == PERF_ATTR_U - ||e->pattrs[i].idx == PERF_ATTR_K - ||e->pattrs[i].idx == PERF_ATTR_H - ||e->pattrs[i].idx == PERF_ATTR_PR) + if (e->pattrs[i].idx == PERF_ATTR_PR) compact = 1; } diff --git a/src/libpfm4/lib/pfmlib_arm_priv.h b/src/libpfm4/lib/pfmlib_arm_priv.h index 60ffed4..ef367b7 100644 --- a/src/libpfm4/lib/pfmlib_arm_priv.h +++ b/src/libpfm4/lib/pfmlib_arm_priv.h @@ -37,14 +37,18 @@ typedef struct { const char *name; /* event name */ const char *desc; /* event description */ unsigned int code; /* event code */ + unsigned int modmsk; /* modifiers bitmask */ } arm_entry_t; typedef union pfm_arm_reg { unsigned int val; /* complete register value */ - struct { - unsigned int sel:8; /* counter */ - unsigned int reserved:24; + unsigned int sel:8; + unsigned int reserved1:19; + unsigned int excl_hyp:1; + unsigned int reserved2:2; + unsigned int excl_pl1:1; + unsigned int excl_usr:1; } evtsel; } pfm_arm_reg_t; @@ -69,4 +73,25 @@ extern unsigned int pfm_arm_get_event_nattrs(void *this, int pidx); extern void pfm_arm_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); extern int pfm_arm_get_perf_encoding(void *this, pfmlib_event_desc_t *e); +#define ARM_ATTR_K 0 /* pl1 priv level */ +#define ARM_ATTR_U 1 /* user priv level */ +#define ARM_ATTR_HV 2 /* hypervisor priv level */ + +#define _ARM_ATTR_K (1 << ARM_ATTR_K) +#define _ARM_ATTR_U (1 << ARM_ATTR_U) +#define _ARM_ATTR_HV (1 << ARM_ATTR_HV) + +#define ARM_ATTR_PLM_ALL (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) + +#define ARMV7_A15_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) +#define ARMV7_A15_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH) + +static inline int +arm_has_plm(void *this, pfmlib_event_desc_t *e) +{ + const arm_entry_t *pe = this_pe(this); + + return pe[e->event].modmsk & ARM_ATTR_PLM_ALL; +} + #endif /* __PFMLIB_ARM_PRIV_H__ */ diff --git a/src/libpfm4/lib/pfmlib_common.c b/src/libpfm4/lib/pfmlib_common.c index 537c2f3..64cb9e8 100644 --- a/src/libpfm4/lib/pfmlib_common.c +++ b/src/libpfm4/lib/pfmlib_common.c @@ -85,8 +85,32 @@ static pfmlib_pmu_t *pfmlib_pmus[]= &intel_wsm_dp_support, &intel_wsm_unc_support, &intel_snb_support, + &intel_snb_unc_cbo0_support, + &intel_snb_unc_cbo1_support, + &intel_snb_unc_cbo2_support, + &intel_snb_unc_cbo3_support, &intel_snb_ep_support, &intel_ivb_support, + &intel_snbep_unc_cb0_support, + &intel_snbep_unc_cb1_support, + &intel_snbep_unc_cb2_support, + &intel_snbep_unc_cb3_support, + &intel_snbep_unc_cb4_support, + &intel_snbep_unc_cb5_support, + &intel_snbep_unc_cb6_support, + &intel_snbep_unc_cb7_support, + &intel_snbep_unc_ha_support, + &intel_snbep_unc_imc0_support, + &intel_snbep_unc_imc1_support, + &intel_snbep_unc_imc2_support, + &intel_snbep_unc_imc3_support, + &intel_snbep_unc_pcu_support, + &intel_snbep_unc_qpi0_support, + &intel_snbep_unc_qpi1_support, + &intel_snbep_unc_ubo_support, + &intel_snbep_unc_r2pcie_support, + &intel_snbep_unc_r3qpi0_support, + &intel_snbep_unc_r3qpi1_support, &intel_x86_arch_support, /* must always be last for x86 */ #endif @@ -126,6 +150,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= #ifdef CONFIG_PFMLIB_ARCH_ARM &arm_cortex_a8_support, &arm_cortex_a9_support, + &arm_cortex_a15_support, #endif #ifdef __linux__ &perf_event_support, @@ -1037,7 +1062,7 @@ found: for (i = 0; i < d->nattrs; i++) { pfm_event_attr_info_t *a = attr(d, i); if (a->type != PFM_ATTR_RAW_UMASK) - DPRINT("%d %d %d %s\n", d->event, i, a->idx, d->pattrs[a->idx].name); + DPRINT("%d %d %d %s\n", d->event, i, a->idx, d->pattrs[d->attrs[i].id].name); else DPRINT("%d %d RAW_UMASK (0x%x)\n", d->event, i, a->idx); } @@ -1280,6 +1305,10 @@ pfmlib_pmu_validate_encoding(pfmlib_pmu_t *pmu, FILE *fp) sprintf(buf, "%s::%s:%s", pmu->name, einfo.name, ainfo.name); ret = pfmlib_validate_encoding(buf, PFM_PLM3|PFM_PLM0); if (ret != PFM_SUCCESS) { + if (pmu->can_auto_encode) { + if (!pmu->can_auto_encode(pmu, i, u)) + continue; + } /* * some PMU may not support raw encoding */ @@ -1295,6 +1324,10 @@ pfmlib_pmu_validate_encoding(pfmlib_pmu_t *pmu, FILE *fp) sprintf(buf, "%s::%s", pmu->name, einfo.name); ret = pfmlib_validate_encoding(buf, PFM_PLM3|PFM_PLM0); if (ret != PFM_SUCCESS) { + if (pmu->can_auto_encode) { + if (!pmu->can_auto_encode(pmu, i, u)) + continue; + } if (ret != PFM_ERR_NOTSUPP) { fprintf(fp, "cannot encode event %s : %s\n", buf, pfm_strerror(ret)); retval = ret; diff --git a/src/libpfm4/lib/pfmlib_intel_nhm_unc.c b/src/libpfm4/lib/pfmlib_intel_nhm_unc.c index aa3df08..c315259 100644 --- a/src/libpfm4/lib/pfmlib_intel_nhm_unc.c +++ b/src/libpfm4/lib/pfmlib_intel_nhm_unc.c @@ -116,6 +116,7 @@ pfm_nhm_unc_get_encoding(void *this, pfmlib_event_desc_t *e) pfm_event_attr_info_t *a; const intel_x86_entry_t *pe = this_pe(this); unsigned int grpmsk, ugrpmsk = 0; + int umodmsk = 0, modmsk_r = 0; uint64_t val; uint64_t umask; unsigned int modhw = 0; @@ -140,6 +141,8 @@ pfm_nhm_unc_get_encoding(void *this, pfmlib_event_desc_t *e) /* take into account hardcoded umask */ umask = (val >> 8) & 0xff; + modmsk_r = pe[e->event].modmsk_req; + for(k=0; k < e->nattrs; k++) { a = attr(e, k); @@ -185,6 +188,9 @@ pfm_nhm_unc_get_encoding(void *this, pfmlib_event_desc_t *e) ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; reg.val |= umask << 8; + + modmsk_r |= pe[e->event].umasks[a->idx].umodmsk_req; + } else if (a->type == PFM_ATTR_RAW_UMASK) { /* there can only be one RAW_UMASK per event */ @@ -202,18 +208,22 @@ pfm_nhm_unc_get_encoding(void *this, pfmlib_event_desc_t *e) switch(a->idx) { case NHM_UNC_ATTR_I: /* invert */ reg.nhm_unc.usel_inv = !!ival; + umodmsk |= _NHM_UNC_ATTR_I; break; case NHM_UNC_ATTR_E: /* edge */ reg.nhm_unc.usel_edge = !!ival; + umodmsk |= _NHM_UNC_ATTR_E; break; case NHM_UNC_ATTR_C: /* counter-mask */ /* already forced, cannot overwrite */ if (ival > 255) return PFM_ERR_INVAL; reg.nhm_unc.usel_cnt_mask = ival; + umodmsk |= _NHM_UNC_ATTR_C; break; case NHM_UNC_ATTR_O: /* occupancy */ reg.nhm_unc.usel_occ = !!ival; + umodmsk |= _NHM_UNC_ATTR_O; break; } } @@ -238,6 +248,12 @@ pfm_nhm_unc_get_encoding(void *this, pfmlib_event_desc_t *e) if (ret != PFM_SUCCESS) return ret; } + + if (modmsk_r && (umodmsk ^ modmsk_r)) { + DPRINT("required modifiers missing: 0x%x\n", modmsk_r); + return PFM_ERR_ATTR; + } + evt_strcat(e->fstr, "%s", pe[e->event].name); pfmlib_sort_attr(e); for(k=0; k < e->nattrs; k++) { diff --git a/src/libpfm4/lib/pfmlib_intel_snb_unc.c b/src/libpfm4/lib/pfmlib_intel_snb_unc.c new file mode 100644 index 0000000..f4bfaba --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snb_unc.c @@ -0,0 +1,84 @@ +/* + * pfmlib_intel_snb_unc.c : Intel SandyBridge C-Box uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" + +#define INTEL_SNB_UNC_ATTRS \ + (_INTEL_X86_ATTR_I|_INTEL_X86_ATTR_E|_INTEL_X86_ATTR_C) + +#include "events/intel_snb_unc_events.h" + +static int +pfm_snb_unc_detect(void *this) +{ + int ret; + + ret = pfm_intel_x86_detect(); + if (ret != PFM_SUCCESS) + return ret; + + if (pfm_intel_x86_cfg.family != 6) + return PFM_ERR_NOTSUPP; + + switch (pfm_intel_x86_cfg.model) { + case 42: /* Sandy Bridge (Core i7 26xx, 25xx) */ + break; + default: + return PFM_ERR_NOTSUPP; + } + return PFM_SUCCESS; +} + +#define SNB_UNC_CBOX(n, p) \ +pfmlib_pmu_t intel_snb_unc_cbo##n##_support={ \ + .desc = "Intel Sandy Bridge C-box"#n" uncore", \ + .name = "snb_unc_cbo"#n, \ + .perf_name = "uncore_cbox_"#n, \ + .pmu = PFM_PMU_INTEL_SNB_UNC_CB##n, \ + .pme_count = LIBPFM_ARRAY_SIZE(intel_snb_unc_##p##_pe), \ + .type = PFM_PMU_TYPE_UNCORE, \ + .num_cntrs = 2, \ + .num_fixed_cntrs = 1, \ + .max_encoding = 1,\ + .pe = intel_snb_unc_##p##_pe, \ + .atdesc = intel_x86_mods, \ + .flags = PFMLIB_PMU_FL_RAW_UMASK, \ + .pmu_detect = pfm_snb_unc_detect, \ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, \ + PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), \ + .get_event_first = pfm_intel_x86_get_event_first, \ + .get_event_next = pfm_intel_x86_get_event_next, \ + .event_is_valid = pfm_intel_x86_event_is_valid, \ + .validate_table = pfm_intel_x86_validate_table, \ + .get_event_info = pfm_intel_x86_get_event_info, \ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ +} + +SNB_UNC_CBOX(0, cbo0); +SNB_UNC_CBOX(1, cbo); +SNB_UNC_CBOX(2, cbo); +SNB_UNC_CBOX(3, cbo); diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc.c new file mode 100644 index 0000000..ea8d322 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc.c @@ -0,0 +1,588 @@ +/* + * pfmlib_intel_snbep_unc.c : Intel SandyBridge-EP uncore PMU common code + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" + +const pfmlib_attr_desc_t snbep_unc_mods[]={ + PFM_ATTR_B("e", "edge detect"), /* edge */ + PFM_ATTR_B("i", "invert"), /* invert */ + PFM_ATTR_I("t", "threshold in range [0-255]"), /* threshold */ + PFM_ATTR_I("t", "threshold in range [0-15]"), /* threshold */ + PFM_ATTR_I("tf", "thread id filter [0-1]"), /* thread id */ + PFM_ATTR_I("cf", "core id filter [0-7]"), /* core id */ + PFM_ATTR_I("nf", "node id bitmask filter [0-255]"),/* nodeid mask */ + PFM_ATTR_I("ff", "frequency >= 100Mhz * [0-255]"),/* freq filter */ + PFM_ATTR_I("addr", "physical address matcher [40 bits]"),/* address matcher */ + PFM_ATTR_NULL +}; + +int +pfm_intel_snbep_unc_detect(void *this) +{ + int ret; + + ret = pfm_intel_x86_detect(); + if (ret != PFM_SUCCESS) + + if (pfm_intel_x86_cfg.family != 6) + return PFM_ERR_NOTSUPP; + + switch(pfm_intel_x86_cfg.model) { + case 45: /* SandyBridge-EP */ + break; + default: + return PFM_ERR_NOTSUPP; + } + return PFM_SUCCESS; +} + +static void +display_cbox(void *this, const char *msg, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t f; + + __pfm_vbprintf("[UNC_%s=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d tid_en=%d] %s\n", + msg, + reg.val, + reg.cbo.unc_event, + reg.cbo.unc_umask, + reg.cbo.unc_en, + reg.cbo.unc_inv, + reg.cbo.unc_edge, + reg.cbo.unc_thres, + reg.cbo.unc_tid, + pe[e->event].name); + + if (e->count == 1) + return; + + f.val = e->codes[1]; + + __pfm_vbprintf("[UNC_CBOX_FILTER=0x%"PRIx64" tid=%d core=0x%x nid=0x%x" + " state=0x%x opc=0x%x]\n", + f.val, + f.cbo_filt.tid, + f.cbo_filt.cid, + f.cbo_filt.nid, + f.cbo_filt.state, + f.cbo_filt.opc); +} + +static void +display_com(void *this, const char *msg, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg) +{ + const intel_x86_entry_t *pe = this_pe(this); + + __pfm_vbprintf("[UNC_%s=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + msg, + reg.val, + reg.com.unc_event, + reg.com.unc_umask, + reg.com.unc_en, + reg.com.unc_inv, + reg.com.unc_edge, + reg.com.unc_thres, + pe[e->event].name); +} + +static void +display_qpi(void *this, const char *msg, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg) +{ + const intel_x86_entry_t *pe = this_pe(this); + + __pfm_vbprintf("[UNC_%s=0x%"PRIx64" event=0x%x sel_ext=%d umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + msg, + reg.val, + reg.qpi.unc_event, + reg.qpi.unc_event_ext, + reg.qpi.unc_umask, + reg.qpi.unc_en, + reg.qpi.unc_inv, + reg.qpi.unc_edge, + reg.qpi.unc_thres, + pe[e->event].name); +} + +static void +display_pcu(void *this, const char *msg, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t f; + + __pfm_vbprintf("[UNC_%s=0x%"PRIx64" event=0x%x occ_sel=0x%x en=%d " + "inv=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s\n", + msg, + reg.val, + reg.pcu.unc_event, + reg.pcu.unc_occ, + reg.pcu.unc_en, + reg.pcu.unc_inv, + reg.pcu.unc_edge, + reg.pcu.unc_thres, + reg.pcu.unc_occ_inv, + reg.pcu.unc_occ_edge, + pe[e->event].name); + + if (e->count == 1) + return; + + f.val = e->codes[1]; + + __pfm_vbprintf("[UNC_PCU_FILTER=0x%"PRIx64" band0=%u band1=%u band2=%u band3=%u]\n", + f.val, + f.pcu_filt.filt0, + f.pcu_filt.filt1, + f.pcu_filt.filt2, + f.pcu_filt.filt3); +} + +static void +display_ha(void *this, const char *msg, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t f; + + __pfm_vbprintf("[UNC_%s=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + msg, + reg.val, + reg.com.unc_event, + reg.com.unc_umask, + reg.com.unc_en, + reg.com.unc_inv, + reg.com.unc_edge, + reg.com.unc_thres, + pe[e->event].name); + + if (e->count == 1) + return; + + f.val = e->codes[1]; + __pfm_vbprintf("[UNC_HA_ADDR=0x%"PRIx64" lo_addr=0x%x hi_addr=0x%x]\n", + f.val, + f.ha_addr.lo_addr, + f.ha_addr.hi_addr); + + f.val = e->codes[2]; + __pfm_vbprintf("[UNC_HA_OPC=0x%"PRIx64" opc=0x%x]\n", f.val, f.ha_opc.opc); +} + + + +#define SNBEP_UNC_DISP(a, b) { .name = a, .disp = b } +static const struct { + const char *name; + void (*disp)(void *this, const char *msg, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg); +} snbep_unc_disp[] = { + SNBEP_UNC_DISP("CBOX0", display_cbox), + SNBEP_UNC_DISP("CBOX1", display_cbox), + SNBEP_UNC_DISP("CBOX2", display_cbox), + SNBEP_UNC_DISP("CBOX3", display_cbox), + SNBEP_UNC_DISP("CBOX4", display_cbox), + SNBEP_UNC_DISP("CBOX5", display_cbox), + SNBEP_UNC_DISP("CBOX6", display_cbox), + SNBEP_UNC_DISP("CBOX7", display_cbox), + SNBEP_UNC_DISP("HA", display_ha), + SNBEP_UNC_DISP("IMC0", display_com), + SNBEP_UNC_DISP("IMC1", display_com), + SNBEP_UNC_DISP("IMC2", display_com), + SNBEP_UNC_DISP("IMC3", display_com), + SNBEP_UNC_DISP("PCU", display_pcu), + SNBEP_UNC_DISP("QPI0", display_qpi), + SNBEP_UNC_DISP("QPI1", display_qpi), + SNBEP_UNC_DISP("UBOX", display_com), + SNBEP_UNC_DISP("R2PCIE", display_com), + SNBEP_UNC_DISP("R3QPI0", display_com), + SNBEP_UNC_DISP("R3QPI1", display_com), +}; + +static void +display_reg(void *this, pfmlib_event_desc_t *e, pfm_snbep_unc_reg_t reg) +{ + pfmlib_pmu_t *pmu = this; + int idx = pmu->pmu - PFM_PMU_INTEL_SNBEP_UNC_CB0; + snbep_unc_disp[idx].disp(this, snbep_unc_disp[idx].name, e, reg); +} + +static inline int +is_occ_event(void *this, int idx) +{ + const intel_x86_entry_t *pe = this_pe(this); + return pe[idx].code & 0x80; +} + +static inline int +get_pcu_filt_band(void *this, pfm_snbep_unc_reg_t reg) +{ +#define PCU_FREQ_BAND0_CODE 0xb /* event code for UNC_P_FREQ_BAND0_CYCLES */ + return reg.pcu.unc_event - PCU_FREQ_BAND0_CODE; +} + +/* + * common encoding routine + */ +int +pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) +{ + const intel_x86_entry_t *pe = this_pe(this); + unsigned int grpmsk, ugrpmsk = 0; + unsigned int max_grpid = INTEL_X86_MAX_GRPID; + unsigned int last_grpid = INTEL_X86_MAX_GRPID; + int umodmsk = 0, modmsk_r = 0; + int pcu_filt_band = -1; + pfm_snbep_unc_reg_t reg; + pfm_snbep_unc_reg_t filter; + pfm_snbep_unc_reg_t addr; + pfm_event_attr_info_t *a; + uint64_t val, umask1, umask2; + int k, ret; + int has_cbo_tid = 0; + unsigned int grpid; + int grpcounts[INTEL_X86_NUM_GRP]; + int ncombo[INTEL_X86_NUM_GRP]; + char umask_str[PFMLIB_EVT_MAX_NAME_LEN]; + + memset(grpcounts, 0, sizeof(grpcounts)); + memset(ncombo, 0, sizeof(ncombo)); + + filter.val = 0; + addr.val = 0; + + pe = this_pe(this); + + umask_str[0] = e->fstr[0] = '\0'; + + reg.val = val = pe[e->event].code; + + /* take into account hardcoded umask */ + umask1 = (val >> 8) & 0xff; + umask2 = umask1; + + grpmsk = (1 << pe[e->event].ngrp)-1; + + modmsk_r = pe[e->event].modmsk_req; + + for(k=0; k < e->nattrs; k++) { + a = attr(e, k); + + if (a->ctrl != PFM_ATTR_CTRL_PMU) + continue; + + if (a->type == PFM_ATTR_UMASK) { + uint64_t um; + + grpid = pe[e->event].umasks[a->idx].grpid; + + /* + * certain event groups are meant to be + * exclusive, i.e., only unit masks of one group + * can be used + */ + if (last_grpid != INTEL_X86_MAX_GRPID && grpid != last_grpid + && intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) { + DPRINT("exclusive unit mask group error\n"); + return PFM_ERR_FEATCOMB; + } + + /* + * selecting certain umasks in a group may exclude any umasks + * from any groups with a higher index + * + * enforcement requires looking at the grpid of all the umasks + */ + if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_EXCL_GRP_GT)) + max_grpid = grpid; + + /* + * certain event groups are meant to be + * exclusive, i.e., only unit masks of one group + * can be used + */ + if (last_grpid != INTEL_X86_MAX_GRPID && grpid != last_grpid + && intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) { + DPRINT("exclusive unit mask group error\n"); + return PFM_ERR_FEATCOMB; + } + /* + * upper layer has removed duplicates + * so if we come here more than once, it is for two + * disinct umasks + * + * NCOMBO=no combination of unit masks within the same + * umask group + */ + ++grpcounts[grpid]; + + /* mark that we have a umask with NCOMBO in this group */ + if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_NCOMBO)) + ncombo[grpid] = 1; + + /* + * if more than one umask in this group but one is marked + * with ncombo, then fail. It is okay to combine umask within + * a group as long as none is tagged with NCOMBO + */ + if (grpcounts[grpid] > 1 && ncombo[grpid]) { + DPRINT("umask %s does not support unit mask combination within group %d\n", pe[e->event].umasks[a->idx].uname, grpid); + return PFM_ERR_FEATCOMB; + } + + last_grpid = grpid; + + um = pe[e->event].umasks[a->idx].ucode; + if (um & ~((1ULL << 32)-1)) { + filter.val |= um >> 32; + um &= (1ULL << 32) - 1; + } + um >>= 8; + umask2 |= um; + ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; + + /* PCU occ event */ + if (is_occ_event(this, e->event)) { + reg.pcu.unc_occ = umask2 >> 6; + umask2 = 0; + } else + reg.val |= umask2 << 8; + + evt_strcat(umask_str, ":%s", pe[e->event].umasks[a->idx].uname); + + modmsk_r |= pe[e->event].umasks[a->idx].umodmsk_req; + + } else if (a->type == PFM_ATTR_RAW_UMASK) { + + /* there can only be one RAW_UMASK per event */ + + /* sanity check */ + if (a->idx & ~0xff) { + DPRINT("raw umask is 8-bit wide\n"); + return PFM_ERR_ATTR; + } + /* override umask */ + umask2 = a->idx & 0xff; + ugrpmsk = grpmsk; + } else { + uint64_t ival = e->attrs[k].ival; + switch(a->idx) { + case SNBEP_UNC_ATTR_I: /* invert */ + if (is_occ_event(this, e->event)) + reg.pcu.unc_occ_inv = !!ival; + else + reg.com.unc_inv = !!ival; + umodmsk |= _SNBEP_UNC_ATTR_I; + break; + case SNBEP_UNC_ATTR_E: /* edge */ + if (is_occ_event(this, e->event)) + reg.pcu.unc_occ_edge = !!ival; + else + reg.com.unc_edge = !!ival; + umodmsk |= _SNBEP_UNC_ATTR_E; + break; + case SNBEP_UNC_ATTR_T8: /* counter-mask */ + /* already forced, cannot overwrite */ + if (ival > 255) + return PFM_ERR_ATTR_VAL; + reg.com.unc_thres = ival; + umodmsk |= _SNBEP_UNC_ATTR_T8; + break; + case SNBEP_UNC_ATTR_T4: /* pcu counter-mask */ + /* already forced, cannot overwrite */ + if (ival > 15) + return PFM_ERR_ATTR_VAL; + reg.pcu.unc_thres = ival; + umodmsk |= _SNBEP_UNC_ATTR_T4; + break; + case SNBEP_UNC_ATTR_TF: /* thread id */ + if (ival > 1) { + DPRINT("invalid thread id, must be < 1"); + return PFM_ERR_ATTR_VAL; + } + reg.cbo.unc_tid = 1; + has_cbo_tid = 1; + filter.cbo_filt.tid = ival; + umodmsk |= _SNBEP_UNC_ATTR_TF; + break; + case SNBEP_UNC_ATTR_CF: /* core id */ + if (ival > 7) + return PFM_ERR_ATTR_VAL; + reg.cbo.unc_tid = 1; + filter.cbo_filt.cid = ival; + has_cbo_tid = 1; + umodmsk |= _SNBEP_UNC_ATTR_CF; + break; + case SNBEP_UNC_ATTR_NF: /* node id */ + if (ival > 255 || ival == 0) { + DPRINT("invalid nf, 0 < nf < 256\n"); + return PFM_ERR_ATTR_VAL; + } + filter.cbo_filt.nid = ival; + umodmsk |= _SNBEP_UNC_ATTR_NF; + break; + case SNBEP_UNC_ATTR_FF: /* freq band filter */ + if (ival > 255) + return PFM_ERR_ATTR_VAL; + pcu_filt_band = get_pcu_filt_band(this, reg); + filter.val = ival << (pcu_filt_band * 8); + umodmsk |= _SNBEP_UNC_ATTR_FF; + break; + case SNBEP_UNC_ATTR_A: /* addr filter */ + if (ival & ~((1ULL << 40)-1)) { + DPRINT("address filter 40bits max\n"); + return PFM_ERR_ATTR_VAL; + } + addr.ha_addr.lo_addr = ival; /* LSB 26 bits */ + addr.ha_addr.hi_addr = (ival >> 26) & ((1ULL << 14)-1); + umodmsk |= _SNBEP_UNC_ATTR_A; + break; + } + } + } + /* + * check that there is at least of unit mask in each unit mask group + */ + if (pe[e->event].numasks && (ugrpmsk != grpmsk || ugrpmsk == 0)) { + uint64_t um = 0; + ugrpmsk ^= grpmsk; + ret = pfm_intel_x86_add_defaults(this, e, ugrpmsk, &um, max_grpid); + if (ret != PFM_SUCCESS) + return ret; + + /* handles filter encoding in umasks */ + if (um & ~((1ULL << (32-8))-1)) { + filter.val |= um >> (32-8); + um &= (1ULL << (32-8)) - 1; + } + um >>= 8; + umask2 = um; + } + + /* + * nf= is only required on some events in CBO + */ + if (!(modmsk_r & _SNBEP_UNC_ATTR_NF) && (umodmsk & _SNBEP_UNC_ATTR_NF)) { + DPRINT("using nf= on an umask which does not require it\n"); + return PFM_ERR_ATTR; + } + + if (modmsk_r && (umodmsk ^ modmsk_r)) { + DPRINT("required modifiers missing: 0x%x\n", modmsk_r); + return PFM_ERR_ATTR; + } + + evt_strcat(e->fstr, "%s", pe[e->event].name); + pfmlib_sort_attr(e); + + for(k = 0; k < e->nattrs; k++) { + a = attr(e, k); + if (a->ctrl != PFM_ATTR_CTRL_PMU) + continue; + if (a->type == PFM_ATTR_UMASK) + evt_strcat(e->fstr, ":%s", pe[e->event].umasks[a->idx].uname); + else if (a->type == PFM_ATTR_RAW_UMASK) + evt_strcat(e->fstr, ":0x%x", a->idx); + } + e->count = 0; + + reg.val |= (umask1 | umask2) << 8; + + e->codes[e->count++] = reg.val; + + /* + * handles C-box filter + */ + if (filter.val || has_cbo_tid) + e->codes[e->count++] = filter.val; + + /* HA address matcher */ + if (addr.val) + e->codes[e->count++] = addr.val; + + for (k = 0; k < e->npattrs; k++) { + int idx; + + if (e->pattrs[k].ctrl != PFM_ATTR_CTRL_PMU) + continue; + + if (e->pattrs[k].type == PFM_ATTR_UMASK) + continue; + + idx = e->pattrs[k].idx; + switch(idx) { + case SNBEP_UNC_ATTR_E: + if (is_occ_event(this, e->event)) + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.pcu.unc_occ_edge); + else + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.com.unc_edge); + break; + case SNBEP_UNC_ATTR_I: + if (is_occ_event(this, e->event)) + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.pcu.unc_occ_inv); + else + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.com.unc_inv); + break; + case SNBEP_UNC_ATTR_T8: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.com.unc_thres); + break; + case SNBEP_UNC_ATTR_T4: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.pcu.unc_thres); + break; + case SNBEP_UNC_ATTR_TF: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.cbo.unc_tid); + break; + case SNBEP_UNC_ATTR_FF: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, (filter.val >> (pcu_filt_band*8)) & 0xff); + break; + case SNBEP_UNC_ATTR_NF: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filter.cbo_filt.nid); + break; + case SNBEP_UNC_ATTR_A: + evt_strcat(e->fstr, ":%s=0x%lx", snbep_unc_mods[idx].name, + addr.ha_addr.hi_addr << 26 | addr.ha_addr.lo_addr); + break; + } + } + display_reg(this, e, reg); + return PFM_SUCCESS; +} + +int +pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx) +{ + if (intel_x86_eflag(this, pidx, INTEL_X86_NO_AUTOENCODE)) + return 0; + + return !intel_x86_uflag(this, pidx, uidx, INTEL_X86_NO_AUTOENCODE); +} diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_cbo.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_cbo.c new file mode 100644 index 0000000..b9c0aab --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_cbo.c @@ -0,0 +1,71 @@ +/* + * pfmlib_intel_snb_unc_cbo.c : Intel SandyBridge-EP C-Box uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_cbo_events.h" + +#define DEFINE_C_BOX(n) \ +pfmlib_pmu_t intel_snbep_unc_cb##n##_support = {\ + .desc = "Intel Sandy Bridge-EP C-Box "#n" uncore",\ + .name = "snbep_unc_cbo"#n,\ + .perf_name = "uncore_cbox_"#n,\ + .pmu = PFM_PMU_INTEL_SNBEP_UNC_CB##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_c_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_snbep_unc_c_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_snbep_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ +} + +DEFINE_C_BOX(0); +DEFINE_C_BOX(1); +DEFINE_C_BOX(2); +DEFINE_C_BOX(3); +DEFINE_C_BOX(4); +DEFINE_C_BOX(5); +DEFINE_C_BOX(6); +DEFINE_C_BOX(7); diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_ha.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_ha.c new file mode 100644 index 0000000..f363938 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_ha.c @@ -0,0 +1,60 @@ +/* + * pfmlib_intel_snb_unc_ha.c : Intel SandyBridge-EP Home Agent (HA) uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_ha_events.h" + +pfmlib_pmu_t intel_snbep_unc_ha_support = { + .desc = "Intel Sandy Bridge-EP HA uncore", + .name = "snbep_unc_ha", + .perf_name = "uncore_ha", + .pmu = PFM_PMU_INTEL_SNBEP_UNC_HA, + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_h_pe), + .type = PFM_PMU_TYPE_UNCORE, + .num_cntrs = 4, + .num_fixed_cntrs = 0, + .max_encoding = 3, /* address matchers */ + .pe = intel_snbep_unc_h_pe, + .atdesc = snbep_unc_mods, + .flags = PFMLIB_PMU_FL_RAW_UMASK, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), + .get_event_first = pfm_intel_x86_get_event_first, + .get_event_next = pfm_intel_x86_get_event_next, + .event_is_valid = pfm_intel_x86_event_is_valid, + .validate_table = pfm_intel_x86_validate_table, + .get_event_info = pfm_intel_x86_get_event_info, + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, +}; diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_imc.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_imc.c new file mode 100644 index 0000000..35bfa69 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_imc.c @@ -0,0 +1,66 @@ +/* + * pfmlib_intel_snbep_unc_imc.c : Intel SandyBridge-EP Integrated Memory Controller (IMC) uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_imc_events.h" + +#define DEFINE_IMC_BOX(n) \ +pfmlib_pmu_t intel_snbep_unc_imc##n##_support = { \ + .desc = "Intel Sandy Bridge-EP IMC"#n" uncore", \ + .name = "snbep_unc_imc"#n, \ + .perf_name = "uncore_imc_"#n, \ + .pmu = PFM_PMU_INTEL_SNBEP_UNC_IMC##n, \ + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_m_pe), \ + .type = PFM_PMU_TYPE_UNCORE, \ + .num_cntrs = 4, \ + .num_fixed_cntrs = 1, \ + .max_encoding = 1, \ + .pe = intel_snbep_unc_m_pe, \ + .atdesc = snbep_unc_mods, \ + .flags = PFMLIB_PMU_FL_RAW_UMASK, \ + .pmu_detect = pfm_intel_snbep_unc_detect, \ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ + .get_event_first = pfm_intel_x86_get_event_first, \ + .get_event_next = pfm_intel_x86_get_event_next, \ + .event_is_valid = pfm_intel_x86_event_is_valid, \ + .validate_table = pfm_intel_x86_validate_table, \ + .get_event_info = pfm_intel_x86_get_event_info, \ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ +}; + +DEFINE_IMC_BOX(0); +DEFINE_IMC_BOX(1); +DEFINE_IMC_BOX(2); +DEFINE_IMC_BOX(3); diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_pcu.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_pcu.c new file mode 100644 index 0000000..91e5bb8 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_pcu.c @@ -0,0 +1,61 @@ +/* + * pfmlib_intel_snbep_unc_pcu.c : Intel SandyBridge-EP Power Control Unit (PCU) uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_pcu_events.h" + +pfmlib_pmu_t intel_snbep_unc_pcu_support = { + .desc = "Intel Sandy Bridge-EP PCU uncore", + .name = "snbep_unc_pcu", + .perf_name = "uncore_pcu", + .pmu = PFM_PMU_INTEL_SNBEP_UNC_PCU, + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_p_pe), + .type = PFM_PMU_TYPE_UNCORE, + .num_cntrs = 4, + .num_fixed_cntrs = 0, + .max_encoding = 2, + .pe = intel_snbep_unc_p_pe, + .atdesc = snbep_unc_mods, + .flags = PFMLIB_PMU_FL_RAW_UMASK, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), + .get_event_first = pfm_intel_x86_get_event_first, + .get_event_next = pfm_intel_x86_get_event_next, + .event_is_valid = pfm_intel_x86_event_is_valid, + .validate_table = pfm_intel_x86_validate_table, + .get_event_info = pfm_intel_x86_get_event_info, + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, + .can_auto_encode = pfm_intel_snbep_unc_can_auto_encode, +}; diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_perf_event.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_perf_event.c new file mode 100644 index 0000000..601806f --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_perf_event.c @@ -0,0 +1,146 @@ +/* pfmlib_intel_snbep_unc_perf.c : perf_events SNB-EP uncore support + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "pfmlib_perf_event_priv.h" + +static int +find_pmu_type_by_name(const char *name) +{ + char filename[PATH_MAX]; + FILE *fp; + int ret, type; + + if (!name) + return PFM_ERR_NOTSUPP; + + sprintf(filename, "/sys/bus/event_source/devices/%s/type", name); + + fp = fopen(filename, "r"); + if (!fp) + return PFM_ERR_NOTSUPP; + + ret = fscanf(fp, "%d", &type); + if (ret != 1) + type = PFM_ERR_NOTSUPP; + + fclose(fp); + + return type; +} + +int +pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) +{ + pfmlib_pmu_t *pmu = this; + struct perf_event_attr *attr = e->os_data; + pfm_intel_x86_reg_t reg; + int ret; + + if (!pmu->get_event_encoding[PFM_OS_NONE]) + return PFM_ERR_NOTSUPP; + + ret = pmu->get_event_encoding[PFM_OS_NONE](this, e); + if (ret != PFM_SUCCESS) + return ret; + + ret = find_pmu_type_by_name(pmu->perf_name); + if (ret < 0) + return ret; + + attr->type = ret; + + reg.val = e->codes[0]; + + attr->config = reg.val; + + /* + * various filters + */ + if (e->count == 2) + attr->config1 = e->codes[1]; + + if (e->count == 3) + attr->config2 = e->codes[2]; + + /* + * uncore measures at all priv levels + * + * user cannot set per-event priv levels because + * attributes are simply not there + * + * dfl_plm is ignored in this case + */ + attr->exclude_hv = 0; + attr->exclude_kernel = 0; + attr->exclude_user = 0; + + return PFM_SUCCESS; +} + +void +pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) +{ + int i, compact; + + for (i = 0; i < e->npattrs; i++) { + compact = 0; + /* umasks never conflict */ + if (e->pattrs[i].type == PFM_ATTR_UMASK) + continue; + + if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { + + /* No precise sampling mode for uncore */ + if (e->pattrs[i].idx == PERF_ATTR_PR) + compact = 1; + + /* + * No hypervisor for uncore + */ + if (e->pattrs[i].idx == PERF_ATTR_H) + compact = 1; + + /* + * uncore has no priv level support + */ + if ( e->pattrs[i].idx == PERF_ATTR_U + || e->pattrs[i].idx == PERF_ATTR_K) + compact = 1; + } + + if (compact) { + pfmlib_compact_pattrs(e, i); + i--; + } + } +} diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h b/src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h new file mode 100644 index 0000000..80d3fc2 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h @@ -0,0 +1,179 @@ +/* + * pfmlib_intel_snbep_unc_priv.c : Intel SandyBridge-EP common definitions + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ +#define __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ + +#define SNBEP_UNC_ATTR_E 0 +#define SNBEP_UNC_ATTR_I 1 +#define SNBEP_UNC_ATTR_T8 2 +#define SNBEP_UNC_ATTR_T4 3 +#define SNBEP_UNC_ATTR_TF 4 +#define SNBEP_UNC_ATTR_CF 5 +#define SNBEP_UNC_ATTR_NF 6 +#define SNBEP_UNC_ATTR_FF 7 +#define SNBEP_UNC_ATTR_A 8 + +#define _SNBEP_UNC_ATTR_I (1 << SNBEP_UNC_ATTR_I) +#define _SNBEP_UNC_ATTR_E (1 << SNBEP_UNC_ATTR_E) +#define _SNBEP_UNC_ATTR_T8 (1 << SNBEP_UNC_ATTR_T8) +#define _SNBEP_UNC_ATTR_T4 (1 << SNBEP_UNC_ATTR_T4) +#define _SNBEP_UNC_ATTR_TF (1 << SNBEP_UNC_ATTR_TF) +#define _SNBEP_UNC_ATTR_CF (1 << SNBEP_UNC_ATTR_CF) +#define _SNBEP_UNC_ATTR_NF (1 << SNBEP_UNC_ATTR_NF) +#define _SNBEP_UNC_ATTR_FF (1 << SNBEP_UNC_ATTR_FF) +#define _SNBEP_UNC_ATTR_A (1 << SNBEP_UNC_ATTR_A) + +#define SNBEP_UNC_R3QPI_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +#define SNBEP_UNC_R2PCIE_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +#define SNBEP_UNC_QPI_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +#define SNBEP_UNC_UBO_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +#define SNBEP_UNC_PCU_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T4) + +#define SNBEP_UNC_PCU_BAND_ATTRS \ + (SNBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF) + +#define SNBEP_UNC_IMC_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +#define SNBEP_UNC_CBO_ATTRS \ + (_SNBEP_UNC_ATTR_I |\ + _SNBEP_UNC_ATTR_E |\ + _SNBEP_UNC_ATTR_T8 |\ + _SNBEP_UNC_ATTR_CF |\ + _SNBEP_UNC_ATTR_TF) + +#define SNBEP_UNC_CBO_NID_ATTRS \ + (SNBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF) + +#define SNBEP_UNC_HA_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +#define SNBEP_UNC_HA_OPC_ATTRS \ + (SNBEP_UNC_HA_ATTRS|_SNBEP_UNC_ATTR_A) + +typedef union { + uint64_t val; + struct { + unsigned long unc_event:8; /* event code */ + unsigned long unc_umask:8; /* unit mask */ + unsigned long unc_res1:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ + unsigned long unc_edge:1; /* edge detec */ + unsigned long unc_res2:3; /* reserved */ + unsigned long unc_en:1; /* enable */ + unsigned long unc_inv:1; /* invert counter mask */ + unsigned long unc_thres:8; /* counter mask */ + unsigned long unc_res3:32; /* reserved */ + } com; /* covers common fields for cbox, ha, imc, ubox, r2pcie, r3qpi */ + struct { + unsigned long unc_event:8; /* event code */ + unsigned long unc_umask:8; /* unit mask */ + unsigned long unc_res1:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ + unsigned long unc_edge:1; /* edge detec */ + unsigned long unc_tid:1; /* tid filter enable */ + unsigned long unc_res2:2; /* reserved */ + unsigned long unc_en:1; /* enable */ + unsigned long unc_inv:1; /* invert counter mask */ + unsigned long unc_thres:8; /* counter mask */ + unsigned long unc_res3:32; /* reserved */ + } cbo; /* covers c-box */ + struct { + unsigned long unc_event:8; /* event code */ + unsigned long unc_res1:6; /* reserved */ + unsigned long unc_occ:2; /* occ select */ + unsigned long unc_res2:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ + unsigned long unc_edge:1; /* edge detec */ + unsigned long unc_res3:1; /* reserved */ + unsigned long unc_res4:2; /* reserved */ + unsigned long unc_en:1; /* enable */ + unsigned long unc_inv:1; /* invert counter mask */ + unsigned long unc_thres:5; /* threshold */ + unsigned long unc_res5:1; /* reserved */ + unsigned long unc_occ_inv:1; /* occupancy invert */ + unsigned long unc_occ_edge:1; /* occupancy edge detect */ + unsigned long unc_res6:32; /* reserved */ + } pcu; /* covers pcu */ + struct { + unsigned long unc_event:8; /* event code */ + unsigned long unc_umask:8; /* unit maks */ + unsigned long unc_res1:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ + unsigned long unc_edge:1; /* edge detec */ + unsigned long unc_res2:1; /* reserved */ + unsigned long unc_res3:1; /* reserved */ + unsigned long unc_event_ext:1; /* event code extension */ + unsigned long unc_en:1; /* enable */ + unsigned long unc_inv:1; /* invert counter mask */ + unsigned long unc_thres:8; /* threshold */ + unsigned long unc_res4:32; /* reserved */ + } qpi; /* covers qpi */ + struct { + unsigned long tid:1; + unsigned long cid:3; + unsigned long res0:1; + unsigned long res1:3; + unsigned long res2:2; + unsigned long nid:8; + unsigned long state:5; + unsigned long opc:9; + unsigned long res3:1; + unsigned long res4:32; + } cbo_filt; /* cbox filter */ + struct { + unsigned long filt0:8; /* band0 freq filter */ + unsigned long filt1:8; /* band1 freq filter */ + unsigned long filt2:8; /* band2 freq filter */ + unsigned long filt3:8; /* band3 freq filter */ + unsigned long res1:32; /* reserved */ + } pcu_filt; + struct { + unsigned long res1:6; + unsigned long lo_addr:26; /* lo order 26b */ + unsigned long hi_addr:14; /* hi order 14b */ + unsigned long res2:18; /* reserved */ + } ha_addr; + struct { + unsigned long opc:6; /* opcode match */ + unsigned long res1:58; /* reserved */ + } ha_opc; +} pfm_snbep_unc_reg_t; + +extern void pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); +extern int pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e); +extern const pfmlib_attr_desc_t snbep_unc_mods[]; +extern int pfm_intel_snbep_unc_detect(void *this); +extern int pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); +extern int pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx); +#endif /* __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ */ diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_qpi.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_qpi.c new file mode 100644 index 0000000..c58a8cf --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_qpi.c @@ -0,0 +1,63 @@ +/* + * pfmlib_intel_snbep_qpi.c : Intel SandyBridge-EP QPI uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_qpi_events.h" + +#define DEFINE_QPI_BOX(n) \ +pfmlib_pmu_t intel_snbep_unc_qpi##n##_support = {\ + .desc = "Intel Sandy Bridge-EP QPI"#n" uncore",\ + .name = "snbep_unc_qpi"#n,\ + .perf_name = "uncore_qpi_"#n,\ + .pmu = PFM_PMU_INTEL_SNBEP_UNC_QPI##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_q_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 3,\ + .pe = intel_snbep_unc_q_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_snbep_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ +} +DEFINE_QPI_BOX(0); +DEFINE_QPI_BOX(1); diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_r2pcie.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_r2pcie.c new file mode 100644 index 0000000..1fd3ca8 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_r2pcie.c @@ -0,0 +1,60 @@ +/* + * pfmlib_intel_snbep_r2pcie.c : Intel SandyBridge-EP R2PCIe uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_r2pcie_events.h" + +pfmlib_pmu_t intel_snbep_unc_r2pcie_support = { + .desc = "Intel Sandy Bridge-EP R2PCIe uncore", + .name = "snbep_unc_r2pcie", + .perf_name = "uncore_r2pcie", + .pmu = PFM_PMU_INTEL_SNBEP_UNC_R2PCIE, + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_r2_pe), + .type = PFM_PMU_TYPE_UNCORE, + .num_cntrs = 4, + .num_fixed_cntrs = 0, + .max_encoding = 1, + .pe = intel_snbep_unc_r2_pe, + .atdesc = snbep_unc_mods, + .flags = PFMLIB_PMU_FL_RAW_UMASK, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), + .get_event_first = pfm_intel_x86_get_event_first, + .get_event_next = pfm_intel_x86_get_event_next, + .event_is_valid = pfm_intel_x86_event_is_valid, + .validate_table = pfm_intel_x86_validate_table, + .get_event_info = pfm_intel_x86_get_event_info, + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, +}; diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_r3qpi.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_r3qpi.c new file mode 100644 index 0000000..288abb1 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_r3qpi.c @@ -0,0 +1,63 @@ +/* + * pfmlib_intel_snbep_r3qpi.c : Intel SandyBridge-EP R3QPI uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_r3qpi_events.h" + +#define DEFINE_R3QPI_BOX(n) \ +pfmlib_pmu_t intel_snbep_unc_r3qpi##n##_support = {\ + .desc = "Intel Sandy Bridge-EP R3QPI"#n" uncore", \ + .name = "snbep_unc_r3qpi"#n,\ + .perf_name = "uncore_r3qpi_"#n, \ + .pmu = PFM_PMU_INTEL_SNBEP_UNC_R3QPI##n, \ + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_r3_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 3,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 1,\ + .pe = intel_snbep_unc_r3_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_snbep_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ +} +DEFINE_R3QPI_BOX(0); +DEFINE_R3QPI_BOX(1); diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_ubo.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc_ubo.c new file mode 100644 index 0000000..b9b4585 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_ubo.c @@ -0,0 +1,60 @@ +/* + * pfmlib_intel_snbep_unc_ubo.c : Intel SandyBridge-EP U-Box uncore PMU + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_snbep_unc_ubo_events.h" + +pfmlib_pmu_t intel_snbep_unc_ubo_support = { + .desc = "Intel Sandy Bridge-EP U-Box uncore", + .name = "snbep_unc_ubo", + .perf_name = "uncore_ubox", + .pmu = PFM_PMU_INTEL_SNBEP_UNC_UBOX, + .pme_count = LIBPFM_ARRAY_SIZE(intel_snbep_unc_u_pe), + .type = PFM_PMU_TYPE_UNCORE, + .num_cntrs = 2, + .num_fixed_cntrs = 1, + .max_encoding = 1, + .pe = intel_snbep_unc_u_pe, + .atdesc = snbep_unc_mods, + .flags = PFMLIB_PMU_FL_RAW_UMASK, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), + .get_event_first = pfm_intel_x86_get_event_first, + .get_event_next = pfm_intel_x86_get_event_next, + .event_is_valid = pfm_intel_x86_event_is_valid, + .validate_table = pfm_intel_x86_validate_table, + .get_event_info = pfm_intel_x86_get_event_info, + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, +}; diff --git a/src/libpfm4/lib/pfmlib_intel_x86.c b/src/libpfm4/lib/pfmlib_intel_x86.c index 5196856..614bafb 100644 --- a/src/libpfm4/lib/pfmlib_intel_x86.c +++ b/src/libpfm4/lib/pfmlib_intel_x86.c @@ -380,9 +380,10 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) const intel_x86_entry_t *pe; pfm_intel_x86_reg_t reg; unsigned int grpmsk, ugrpmsk = 0; - uint64_t umask1, umask2; + uint64_t umask1, umask2, ucode, last_ucode = ~0ULL; unsigned int modhw = 0; unsigned int plmmsk = 0; + int umodmsk = 0, modmsk_r = 0; int k, ret, id; unsigned int max_grpid = INTEL_X86_MAX_GRPID; unsigned int last_grpid = INTEL_X86_MAX_GRPID; @@ -409,6 +410,8 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) umask1 = (reg.val >> 8) & 0xff; umask2 = 0; + modmsk_r = pe[e->event].modmsk_req; + for (k = 0; k < e->nattrs; k++) { a = attr(e, k); @@ -462,10 +465,21 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) } last_grpid = grpid; + ucode = pe[e->event].umasks[a->idx].ucode; modhw |= pe[e->event].umasks[a->idx].modhw; - umask2 |= pe[e->event].umasks[a->idx].ucode >> 8; + umask2 |= ucode >> 8; ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; + modmsk_r |= pe[e->event].umasks[a->idx].umodmsk_req; + + if (intel_x86_uflag(this, e->event, a->idx, INTEL_X86_CODE_OVERRIDE)) { + if (last_ucode != ~0ULL && (ucode & 0xff) != last_ucode) { + DPRINT("cannot override event with two different codes for %s\n", pe[e->event].name); + return PFM_ERR_FEATCOMB; + } + last_ucode = ucode & 0xff; + reg.sel_event_select = last_ucode; + } } else if (a->type == PFM_ATTR_RAW_UMASK) { /* there can only be one RAW_UMASK per event */ @@ -485,11 +499,13 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) if (modhw & _INTEL_X86_ATTR_I) return PFM_ERR_ATTR_SET; reg.sel_inv = !!ival; + umodmsk |= _INTEL_X86_ATTR_I; break; case INTEL_X86_ATTR_E: /* edge */ if (modhw & _INTEL_X86_ATTR_E) return PFM_ERR_ATTR_SET; reg.sel_edge = !!ival; + umodmsk |= _INTEL_X86_ATTR_E; break; case INTEL_X86_ATTR_C: /* counter-mask */ if (modhw & _INTEL_X86_ATTR_C) @@ -497,23 +513,27 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) if (ival > 255) return PFM_ERR_ATTR_VAL; reg.sel_cnt_mask = ival; + umodmsk |= _INTEL_X86_ATTR_C; break; case INTEL_X86_ATTR_U: /* USR */ if (modhw & _INTEL_X86_ATTR_U) return PFM_ERR_ATTR_SET; reg.sel_usr = !!ival; plmmsk |= _INTEL_X86_ATTR_U; + umodmsk |= _INTEL_X86_ATTR_U; break; case INTEL_X86_ATTR_K: /* OS */ if (modhw & _INTEL_X86_ATTR_K) return PFM_ERR_ATTR_SET; reg.sel_os = !!ival; plmmsk |= _INTEL_X86_ATTR_K; + umodmsk |= _INTEL_X86_ATTR_K; break; case INTEL_X86_ATTR_T: /* anythread (v3 and above) */ if (modhw & _INTEL_X86_ATTR_T) return PFM_ERR_ATTR_SET; reg.sel_anythr = !!ival; + umodmsk |= _INTEL_X86_ATTR_T; break; } } @@ -524,9 +544,9 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) * then we use the dfl_plm */ if (!(plmmsk & (_INTEL_X86_ATTR_K|_INTEL_X86_ATTR_U))) { - if (e->dfl_plm & PFM_PLM0) + if ((e->dfl_plm & PFM_PLM0) && (pmu->supported_plm & PFM_PLM0)) reg.sel_os = 1; - if (e->dfl_plm & PFM_PLM3) + if ((e->dfl_plm & PFM_PLM3) && (pmu->supported_plm & PFM_PLM3)) reg.sel_usr = 1; } /* @@ -555,6 +575,10 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) } } + if (modmsk_r && (umodmsk ^ modmsk_r)) { + DPRINT("required modifiers missing: 0x%x\n", modmsk_r); + return PFM_ERR_ATTR; + } /* * reorder all the attributes such that the fstr appears always * the same regardless of how the attributes were submitted. @@ -634,16 +658,8 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) int pfm_intel_x86_get_encoding(void *this, pfmlib_event_desc_t *e) { - const intel_x86_entry_t *pe = this_pe(this); int ret; - /* - * If event requires special encoding, then invoke - * model specific encoding function - */ - if (intel_x86_eflag(this, e->event, INTEL_X86_ENCODER)) - return pe[e->event].encoder(this, e); - ret = pfm_intel_x86_encode_gen(this, e); if (ret != PFM_SUCCESS) return ret; @@ -745,9 +761,9 @@ pfm_intel_x86_validate_table(void *this, FILE *fp) for (j=i+1; j < (int)pmu->pme_count; j++) { if (pe[i].code == pe[j].code && !(pe[j].equiv || pe[i].equiv) && pe[j].cntmsk == pe[i].cntmsk) { fprintf(fp, "pmu: %s events %s and %s have the same code 0x%x\n", pmu->name, pe[i].name, pe[j].name, pe[i].code); - error++; + error++; + } } - } for(j=0; j < INTEL_X86_NUM_GRP; j++) ndfl[j] = 0; @@ -863,7 +879,11 @@ pfm_intel_x86_get_event_attr_info(void *this, int pidx, int attr_idx, pfm_event_ info->name = pe[pidx].umasks[idx].uname; info->desc = pe[pidx].umasks[idx].udesc; info->equiv= pe[pidx].umasks[idx].uequiv; - info->code = pe[pidx].umasks[idx].ucode >> 8; /* show actual umask code */ + + info->code = pe[pidx].umasks[idx].ucode; + if (!intel_x86_uflag(this, pidx, idx, INTEL_X86_CODE_OVERRIDE)) + info->code >>= 8; + info->type = PFM_ATTR_UMASK; info->is_dfl = intel_x86_uflag(this, pidx, idx, INTEL_X86_DFL); info->is_precise = intel_x86_uflag(this, pidx, idx, INTEL_X86_PEBS); @@ -949,3 +969,18 @@ pfm_intel_x86_get_event_nattrs(void *this, int pidx) nattrs += intel_x86_num_mods(this, pidx); return nattrs; } + +int +pfm_intel_x86_can_auto_encode(void *this, int pidx, int uidx) +{ + int numasks; + + if (intel_x86_eflag(this, pidx, INTEL_X86_NO_AUTOENCODE)) + return 0; + + numasks = intel_x86_num_umasks(this, pidx); + if (uidx >= numasks) + return 0; + + return !intel_x86_uflag(this, pidx, uidx, INTEL_X86_NO_AUTOENCODE); +} diff --git a/src/libpfm4/lib/pfmlib_intel_x86_perf_event.c b/src/libpfm4/lib/pfmlib_intel_x86_perf_event.c index bbffb48..2aea7fd 100644 --- a/src/libpfm4/lib/pfmlib_intel_x86_perf_event.c +++ b/src/libpfm4/lib/pfmlib_intel_x86_perf_event.c @@ -123,16 +123,15 @@ pfm_intel_nhm_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) /* * encoder treats all events as using the generic - * counters. So here correct fot events that are - * fixed counter only. + * counters. + * perf_events override the enable and int bits, so + * drop them here. + * + * also makes fixed counter special encoding 0xff + * work. kernel checking for perfect match. */ - if (intel_x86_eflag(this, e->event, INTEL_X86_FIXED)) { - reg.nhm_unc_fixed.usel_en = 1; - reg.nhm_unc_fixed.usel_int = 1; - } else { - reg.nhm_unc.usel_en = 1; - reg.nhm_unc.usel_int = 1; - } + reg.nhm_unc.usel_en = 0; + reg.nhm_unc.usel_int = 0; attr->config = reg.val; diff --git a/src/libpfm4/lib/pfmlib_intel_x86_priv.h b/src/libpfm4/lib/pfmlib_intel_x86_priv.h index d53b693..b7a600f 100644 --- a/src/libpfm4/lib/pfmlib_intel_x86_priv.h +++ b/src/libpfm4/lib/pfmlib_intel_x86_priv.h @@ -48,16 +48,12 @@ typedef struct { unsigned int umodel; /* only available on this PMU model */ unsigned int grpid; /* unit mask group id */ unsigned int modhw; /* hardwired modifiers, cannot be changed */ + unsigned int umodmsk_req; /* bitmask of required modifiers */ } intel_x86_umask_t; #define INTEL_X86_MAX_GRPID (~0U) /* - * event-specific encoder (optional) - */ -typedef int (*intel_x86_encoder_t)(void *this, pfmlib_event_desc_t *e); - -/* * event description */ typedef struct { @@ -69,8 +65,8 @@ typedef struct { unsigned int numasks;/* number of umasks */ unsigned int flags; /* flags */ unsigned int modmsk; /* bitmask of modifiers for this event */ + unsigned int modmsk_req; /* bitmask of required modifiers */ unsigned int ngrp; /* number of unit masks groups */ - intel_x86_encoder_t encoder; /* event-specific encoder (optional) */ const intel_x86_umask_t *umasks; /* umask desc */ } intel_x86_entry_t; @@ -80,12 +76,13 @@ typedef struct { #define INTEL_X86_NCOMBO 0x01 /* unit masks within group cannot be combined */ #define INTEL_X86_FALLBACK_GEN 0x02 /* fallback from fixed to generic counter possible */ #define INTEL_X86_PEBS 0x04 /* event supports PEBS or at least one umask supports PEBS */ -#define INTEL_X86_ENCODER 0x08 /* event requires model-specific encoding */ -#define INTEL_X86_DFL 0x10 /* unit mask is default choice */ -#define INTEL_X86_GRP_EXCL 0x20 /* only one unit mask group can be selected */ -#define INTEL_X86_NHM_OFFCORE 0x40 /* Nehalem/Westmere offcore_response */ -#define INTEL_X86_EXCL_GRP_GT 0x80 /* exclude use of grp with id > own grp */ -#define INTEL_X86_FIXED 0x100 /* fixed counter only event */ +#define INTEL_X86_DFL 0x08 /* unit mask is default choice */ +#define INTEL_X86_GRP_EXCL 0x10 /* only one unit mask group can be selected */ +#define INTEL_X86_NHM_OFFCORE 0x20 /* Nehalem/Westmere offcore_response */ +#define INTEL_X86_EXCL_GRP_GT 0x40 /* exclude use of grp with id > own grp */ +#define INTEL_X86_FIXED 0x80 /* fixed counter only event */ +#define INTEL_X86_NO_AUTOENCODE 0x100 /* does not support auto encoding validation */ +#define INTEL_X86_CODE_OVERRIDE 0x200 /* umask overrides event code */ typedef union pfm_intel_x86_reg { unsigned long long val; /* complete register value */ @@ -265,4 +262,6 @@ extern int intel_x86_attr2mod(void *this, int pidx, int attr_idx); extern int pfm_intel_x86_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_intel_nhm_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern void pfm_intel_x86_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); +extern int pfm_intel_x86_can_auto_encode(void *this, int pidx, int uidx); + #endif /* __PFMLIB_INTEL_X86_PRIV_H__ */ diff --git a/src/libpfm4/lib/pfmlib_perf_event_pmu.c b/src/libpfm4/lib/pfmlib_perf_event_pmu.c index 4a633e8..7fc73fa 100644 --- a/src/libpfm4/lib/pfmlib_perf_event_pmu.c +++ b/src/libpfm4/lib/pfmlib_perf_event_pmu.c @@ -905,7 +905,7 @@ pfm_perf_validate_table(void *this, FILE *fp) error++; } - if (perf_pe[i].numasks >= PERF_MAX_UMASKS && perf_pe[i].umask_ovfl_idx == PERF_INVAL_OVFL_IDX) { + if (perf_pe[i].numasks > PERF_MAX_UMASKS && perf_pe[i].umask_ovfl_idx == PERF_INVAL_OVFL_IDX) { fprintf(fp, "pmu: %s event%d: %s :: numasks too big (<%d)\n", name, i, perf_pe[i].name, PERF_MAX_UMASKS); error++; } diff --git a/src/libpfm4/lib/pfmlib_priv.h b/src/libpfm4/lib/pfmlib_priv.h index 00d8c8b..e125c3e 100644 --- a/src/libpfm4/lib/pfmlib_priv.h +++ b/src/libpfm4/lib/pfmlib_priv.h @@ -122,6 +122,7 @@ typedef struct pfmlib_pmu { int (*get_event_info)(void *this, int pidx, pfm_event_info_t *info); unsigned int (*get_event_nattrs)(void *this, int pidx); int (*event_is_valid)(void *this, int pidx); + int (*can_auto_encode)(void *this, int pidx, int uidx); int (*get_event_attr_info)(void *this, int pidx, int umask_idx, pfm_event_attr_info_t *info); int (*get_event_encoding[PFM_OS_MAX])(void *this, pfmlib_event_desc_t *e); @@ -221,8 +222,32 @@ extern pfmlib_pmu_t intel_nhm_support; extern pfmlib_pmu_t intel_nhm_ex_support; extern pfmlib_pmu_t intel_nhm_unc_support; extern pfmlib_pmu_t intel_snb_support; +extern pfmlib_pmu_t intel_snb_unc_cbo0_support; +extern pfmlib_pmu_t intel_snb_unc_cbo1_support; +extern pfmlib_pmu_t intel_snb_unc_cbo2_support; +extern pfmlib_pmu_t intel_snb_unc_cbo3_support; extern pfmlib_pmu_t intel_snb_ep_support; extern pfmlib_pmu_t intel_ivb_support; +extern pfmlib_pmu_t intel_snbep_unc_cb0_support; +extern pfmlib_pmu_t intel_snbep_unc_cb1_support; +extern pfmlib_pmu_t intel_snbep_unc_cb2_support; +extern pfmlib_pmu_t intel_snbep_unc_cb3_support; +extern pfmlib_pmu_t intel_snbep_unc_cb4_support; +extern pfmlib_pmu_t intel_snbep_unc_cb5_support; +extern pfmlib_pmu_t intel_snbep_unc_cb6_support; +extern pfmlib_pmu_t intel_snbep_unc_cb7_support; +extern pfmlib_pmu_t intel_snbep_unc_ha_support; +extern pfmlib_pmu_t intel_snbep_unc_imc0_support; +extern pfmlib_pmu_t intel_snbep_unc_imc1_support; +extern pfmlib_pmu_t intel_snbep_unc_imc2_support; +extern pfmlib_pmu_t intel_snbep_unc_imc3_support; +extern pfmlib_pmu_t intel_snbep_unc_pcu_support; +extern pfmlib_pmu_t intel_snbep_unc_qpi0_support; +extern pfmlib_pmu_t intel_snbep_unc_qpi1_support; +extern pfmlib_pmu_t intel_snbep_unc_ubo_support; +extern pfmlib_pmu_t intel_snbep_unc_r2pcie_support; +extern pfmlib_pmu_t intel_snbep_unc_r3qpi0_support; +extern pfmlib_pmu_t intel_snbep_unc_r3qpi1_support; extern pfmlib_pmu_t power4_support; extern pfmlib_pmu_t ppc970_support; extern pfmlib_pmu_t ppc970mp_support; @@ -246,6 +271,7 @@ extern pfmlib_pmu_t intel_wsm_dp_support; extern pfmlib_pmu_t intel_wsm_unc_support; extern pfmlib_pmu_t arm_cortex_a8_support; extern pfmlib_pmu_t arm_cortex_a9_support; +extern pfmlib_pmu_t arm_cortex_a15_support; extern pfmlib_pmu_t mips_74k_support; extern pfmlib_os_t pfmlib_os_perf; diff --git a/src/libpfm4/libpfm.spec b/src/libpfm4/libpfm.spec index 7781445..84ff2ce 100644 --- a/src/libpfm4/libpfm.spec +++ b/src/libpfm4/libpfm.spec @@ -3,8 +3,8 @@ %define python_prefix %(python -c "import sys; print sys.prefix") Name: libpfm -Version: 4.2.0 -Release: 2%{?dist} +Version: 4.3.0 +Release: 1%{?dist} Summary: Library to encode performance events for use by perf tool @@ -70,6 +70,7 @@ make \ LIBDIR=$RPM_BUILD_ROOT%{_libdir} \ PYTHON_PREFIX=$RPM_BUILD_ROOT/%{python_prefix} \ %{python_config} \ + LDCONFIG=/bin/true \ install %clean @@ -96,6 +97,22 @@ rm -fr $RPM_BUILD_ROOT %endif %changelog +* Tue Aug 28 2012 Stephane Eranian 4.3.0-1 +- ARM Cortex A15 support +- updated Intel Sandy Bridge core PMU events +- Intel Sandy Bridge desktop (model 42) uncore PMU support +- Intel Ivy Bridge support +- full perf_events generic event support +- updated perf_examples +- enabled Intel Nehalem/Westmere uncore PMU support +- AMD LLano processor supoprt (Fam 12h) +- AMD Turion rocessor supoprt (Fam 11h) +- Intel Atom Cedarview processor support +- Win32 compilation support +- perf_events excl attribute +- perf_events generic hw event aliases support +- many bug fixes + * Wed Mar 14 2012 William Cohen 4.2.0-2 - Some spec file fixup. diff --git a/src/libpfm4/perf_examples/notify_group.c b/src/libpfm4/perf_examples/notify_group.c index e3eb8d2..39b64c5 100644 --- a/src/libpfm4/perf_examples/notify_group.c +++ b/src/libpfm4/perf_examples/notify_group.c @@ -194,7 +194,8 @@ error: * destroy our session */ for(i=0; i < num_fds; i++) - close(fds[i].fd); + if (fds[i].fd > -1) + close(fds[i].fd); perf_free_fds(fds, num_fds); diff --git a/src/libpfm4/perf_examples/notify_self.c b/src/libpfm4/perf_examples/notify_self.c index da42aa0..72bb15f 100644 --- a/src/libpfm4/perf_examples/notify_self.c +++ b/src/libpfm4/perf_examples/notify_self.c @@ -177,6 +177,9 @@ main(int argc, char **argv) * PERF_FORMAT_ID: returns unique 64-bit identifier in addition * to event value. */ + if (fds[0].fd == -1) + errx(1, "cannot create event 0"); + ret = read(fds[0].fd, val, sz); if (ret == -1) err(1, "cannot read id %zu", sizeof(val)); diff --git a/src/libpfm4/perf_examples/perf_util.c b/src/libpfm4/perf_examples/perf_util.c index d3e5f64..e2b8864 100644 --- a/src/libpfm4/perf_examples/perf_util.c +++ b/src/libpfm4/perf_examples/perf_util.c @@ -137,13 +137,15 @@ perf_setup_list_events(const char *ev, perf_event_desc_t **fd, int *num_fds) return -1; } - for(i=0, q = events; i < num-2; i++, q = p + 1) { - p = strchr(q, ','); + i = 0; q = events; + while((p = strchr(q, ','))) { *p = '\0'; - argv[i] = q; + argv[i++] = q; + q = p + 1; } argv[i++] = q; argv[i] = NULL; + ret = perf_setup_argv_events(argv, fd, num_fds); free(argv); free(events); /* strdup in perf_setup_argv_events() */ @@ -516,6 +518,7 @@ perf_display_sample(perf_event_desc_t *fds, int num_fds, int idx, struct perf_ev } } else { + time_enabled = time_running = 0; /* * this program does not use FORMAT_GROUP when there is only one event */ diff --git a/src/libpfm4/perf_examples/perf_util.h b/src/libpfm4/perf_examples/perf_util.h index 8005121..6252225 100644 --- a/src/libpfm4/perf_examples/perf_util.h +++ b/src/libpfm4/perf_examples/perf_util.h @@ -31,8 +31,8 @@ typedef struct { struct perf_event_attr hw; - uint64_t value, prev_value; - uint64_t enabled, running; + uint64_t values[3]; + uint64_t prev_values[3]; char *name; uint64_t id; /* event id kernel */ void *buf; @@ -86,6 +86,23 @@ perf_scale(uint64_t *values) return res; } +static inline uint64_t +perf_scale_delta(uint64_t *values, uint64_t *prev_values) +{ + uint64_t res = 0; + + if (!values[2] && !values[1] && values[0]) + warnx("WARNING: time_running = 0 = time_enabled, raw count not zero\n"); + + if (values[2] > values[1]) + warnx("WARNING: time_running > time_enabled\n"); + + if (values[2] - prev_values[2]) + res = (uint64_t)((double)((values[0] - prev_values[0]) * (values[1] - prev_values[1])/ (values[2] - prev_values[2]))); + return res; +} + + /* * TIME_RUNNING/TIME_ENABLED */ diff --git a/src/libpfm4/perf_examples/self_count.c b/src/libpfm4/perf_examples/self_count.c index 362fc5a..90c6c24 100644 --- a/src/libpfm4/perf_examples/self_count.c +++ b/src/libpfm4/perf_examples/self_count.c @@ -127,11 +127,8 @@ read_count(perf_event_desc_t *fds) uint64_t offset = 0; uint64_t val; unsigned int seq; -#if 0 - double ratio; -#endif ssize_t ret; - int idx; + int idx = -1; hdr = fds->buf; @@ -166,17 +163,6 @@ read_count(perf_event_desc_t *fds) values[0] += offset; val = perf_scale(values); -#if 0 - ratio = perf_scale_ratio(values); - - if (ratio == 1.0) - printf("%20"PRIu64" %s (%s)\n", val, fds->name, offset == -1 ? "syscall" : "rdpmc"); - else - if (ratio == 0.0) - printf("%20"PRIu64" %s (did not run: incompatible events, too many events in a group, competing session)\n", val, fds->name); - else - printf("%20"PRIu64" %s (scaled from %.2f%% of time)\n", val, fds->name, ratio*100.0); -#endif return val; } diff --git a/src/libpfm4/perf_examples/syst.c b/src/libpfm4/perf_examples/syst.c index 0325845..196b1ce 100644 --- a/src/libpfm4/perf_examples/syst.c +++ b/src/libpfm4/perf_examples/syst.c @@ -120,7 +120,6 @@ measure(void) } for(l=0; l < options.delay; l++) { - uint64_t values[3]; sleep(1); @@ -128,10 +127,11 @@ measure(void) for(c = cmin; c < cmax; c++) { fds = all_fds[c]; for(i=0; i < num_fds[c]; i++) { + uint64_t val, delta; double ratio; - ret = read(fds[i].fd, values, sizeof(values)); - if (ret != sizeof(values)) { + ret = read(fds[i].fd, fds[i].values, sizeof(fds[i].values)); + if (ret != sizeof(fds[i].values)) { if (ret == -1) err(1, "cannot read event %d:%d", i, ret); else @@ -142,17 +142,20 @@ measure(void) * scaling because we may be sharing the PMU and * thus may be multiplexed */ - fds[i].prev_value = fds[i].value; - fds[i].value = perf_scale(values); - ratio = perf_scale_ratio(values); + val = perf_scale(fds[i].values); + ratio = perf_scale_ratio(fds[i].values); + delta = perf_scale_delta(fds[i].values, fds[i].prev_values); - printf("CPU%d val=%-20"PRIu64" raw=%"PRIu64" ena=%"PRIu64" run=%"PRIu64" ratio=%.2f delta=%-20"PRIu64" %s\n", + printf("CPU%d val=%-20"PRIu64" %-20"PRIu64" raw=%"PRIu64" ena=%"PRIu64" run=%"PRIu64" ratio=%.2f %s\n", c, - fds[i].value, - values[0], - values[1], values[2], ratio, - fds[i].value - fds[i].prev_value, + val, + delta, + fds[i].values[0], + fds[i].values[1], fds[i].values[2], ratio, fds[i].name); + fds[i].prev_values[0] = fds[i].values[0]; + fds[i].prev_values[1] = fds[i].values[1]; + fds[i].prev_values[2] = fds[i].values[2]; } } } diff --git a/src/libpfm4/perf_examples/syst_count.c b/src/libpfm4/perf_examples/syst_count.c index c9af0d9..bad0d73 100644 --- a/src/libpfm4/perf_examples/syst_count.c +++ b/src/libpfm4/perf_examples/syst_count.c @@ -190,7 +190,8 @@ setup_cpu(int cpu, int cfd) return; error: for (i=0; i < j; i++) { - close(fds[i].fd); + if (fds[i].fd > -1) + close(fds[i].fd); fds[i].fd = -1; } } @@ -236,7 +237,7 @@ void stop_cpu(int c) void read_cpu(int c) { perf_event_desc_t *fds; - uint64_t values[3]; + uint64_t val, delta; double ratio; int i, j, n, ret; @@ -249,9 +250,9 @@ void read_cpu(int c) for(i=0, j = 0; i < options.num_groups; i++) { for(n = 0; n < options.nevents[i]; n++, j++) { - memset(values, 0, sizeof(values)); - ret = read(fds[j].fd, values, sizeof(values)); - if (ret != sizeof(values)) { + + ret = read(fds[j].fd, fds[j].values, sizeof(fds[j].values)); + if (ret != sizeof(fds[j].values)) { if (ret == -1) err(1, "cannot read event %s : %d", fds[j].name, ret); else { @@ -263,20 +264,27 @@ void read_cpu(int c) * scaling because we may be sharing the PMU and * thus may be multiplexed */ - fds[j].value = perf_scale(values); - ratio = perf_scale_ratio(values); + delta = perf_scale_delta(fds[j].values, fds[j].prev_values); + val = perf_scale(fds[j].values); + ratio = perf_scale_ratio(fds[j].values); - printf("CPU%-3d G%-2d %'-20"PRIu64" %s (scaling %.2f%%, ena=%'"PRIu64", run=%'"PRIu64") %s\n", + printf("CPU%-3d G%-2d %'-20"PRIu64" %-20"PRIu64" %s (scaling %.2f%%, ena=%'"PRIu64", run=%'"PRIu64") %s\n", c, i, - fds[j].value, + val, + delta, fds[j].name, (1.0-ratio)*100, - values[1], - values[2], + fds[j].values[1], + fds[j].values[2], options.cgroup_name ? options.cgroup_name : ""); - if (values[2] > values[1]) - errx(1, "WARNING: time_running > time_enabled %"PRIu64"\n", values[2] - values[1]); + + fds[j].prev_values[0] = fds[j].values[0]; + fds[j].prev_values[1] = fds[j].values[1]; + fds[j].prev_values[2] = fds[j].values[2]; + + if (fds[j].values[2] > fds[j].values[1]) + errx(1, "WARNING: time_running > time_enabled %"PRIu64"\n", fds[j].values[2] - fds[j].values[1]); } } } diff --git a/src/libpfm4/perf_examples/syst_smpl.c b/src/libpfm4/perf_examples/syst_smpl.c index 0ebeb6a..c54bfe6 100755 --- a/src/libpfm4/perf_examples/syst_smpl.c +++ b/src/libpfm4/perf_examples/syst_smpl.c @@ -118,7 +118,7 @@ setup_cpu(int cpu, int fd) { uint64_t *val; int ret, flags; - int i; + int i, pid; /* * does allocate fds @@ -137,8 +137,10 @@ setup_cpu(int cpu, int fd) if (options.cgroup) { flags = PERF_FLAG_PID_CGROUP; + pid = fd; } else { flags = 0; + pid = -1; } if (options.pin) @@ -164,7 +166,7 @@ setup_cpu(int cpu, int fd) fds[i].hw.sample_type |= PERF_SAMPLE_PERIOD; } - fds[i].fd = perf_event_open(&fds[i].hw, -1, cpu, fds[0].fd, flags); + fds[i].fd = perf_event_open(&fds[i].hw, pid, cpu, fds[0].fd, flags); if (fds[i].fd == -1) { if (fds[i].hw.precise_ip) err(1, "cannot attach event %s: precise mode may not be supported", fds[i].name); @@ -207,14 +209,16 @@ setup_cpu(int cpu, int fd) * We are skipping the first 3 values (nr, time_enabled, time_running) * and then for each event we get a pair of values. */ - if (num_fds > 1) { + if (num_fds > 1 && fds[0].fd > -1) { + ssize_t sret; + sz = (3+2*num_fds)*sizeof(uint64_t); val = malloc(sz); if (!val) err(1, "cannot allocated memory"); - ret = read(fds[0].fd, val, sz); - if (ret == -1) + sret = read(fds[0].fd, val, sz); + if (sret == (ssize_t)sz) err(1, "cannot read id %zu", sizeof(val)); for(i=0; i < num_fds; i++) { @@ -310,6 +314,10 @@ mainloop(char **arg) setup_cpu(options.cpu, fd); + /* done with cgroup */ + if (fd != -1) + close(fd); + signal(SIGALRM, handler); signal(SIGINT, handler); diff --git a/src/libpfm4/perf_examples/task.c b/src/libpfm4/perf_examples/task.c index 38e22f5..392602f 100644 --- a/src/libpfm4/perf_examples/task.c +++ b/src/libpfm4/perf_examples/task.c @@ -120,10 +120,9 @@ read_groups(perf_event_desc_t *fds, int num) * scaling because we may be sharing the PMU and * thus may be multiplexed */ - fds[i].prev_value = fds[i].value; - fds[i].value = perf_scale(values); - fds[i].enabled = values[1]; - fds[i].running = values[2]; + fds[i].values[0] = values[0]; + fds[i].values[1] = values[1]; + fds[i].values[2] = values[2]; } evt += num_evts_to_read; } @@ -134,34 +133,41 @@ read_groups(perf_event_desc_t *fds, int num) static void print_counts(perf_event_desc_t *fds, int num) { + double ratio; + uint64_t val, delta; int i; read_groups(fds, num); for(i=0; i < num; i++) { - double ratio; - uint64_t val; - val = fds[i].value - fds[i].prev_value; - - ratio = 0.0; - if (fds[i].enabled) - ratio = 1.0 * fds[i].running / fds[i].enabled; + val = perf_scale(fds[i].values); + delta = perf_scale_delta(fds[i].values, fds[i].prev_values); + ratio = perf_scale_ratio(fds[i].values); /* separate groups */ if (perf_is_group_leader(fds, i)) putchar('\n'); - if (fds[i].value < fds[i].prev_value) { - printf("inconsistent scaling %s (cur=%'"PRIu64" : prev=%'"PRIu64")\n", fds[i].name, fds[i].value, fds[i].prev_value); - continue; - } - printf("%'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", - val, - fds[i].name, - (1.0-ratio)*100.0, - fds[i].enabled, - fds[i].running); + if (options.print) + printf("%'20"PRIu64" %'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", + val, + delta, + fds[i].name, + (1.0-ratio)*100.0, + fds[i].values[1], + fds[i].values[2]); + else + printf("%'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", + val, + fds[i].name, + (1.0-ratio)*100.0, + fds[i].values[1], + fds[i].values[2]); + + fds[i].prev_values[0] = fds[i].values[0]; + fds[i].prev_values[1] = fds[i].values[1]; + fds[i].prev_values[2] = fds[i].values[2]; } } @@ -179,6 +185,8 @@ parent(char **arg) char buf; pid_t pid; + go[0] = go[1] = -1; + if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed"); @@ -276,7 +284,7 @@ parent(char **arg) } } - if (!options.pid) + if (!options.pid && go[1] > -1) close(go[1]); if (options.print) { diff --git a/src/libpfm4/perf_examples/task_attach_timeout.c b/src/libpfm4/perf_examples/task_attach_timeout.c index b524018..7fc5524 100644 --- a/src/libpfm4/perf_examples/task_attach_timeout.c +++ b/src/libpfm4/perf_examples/task_attach_timeout.c @@ -53,7 +53,6 @@ static options_t options; static void print_counts(perf_event_desc_t *fds, int num, int do_delta) { - uint64_t values[3]; ssize_t ret; int i; @@ -64,23 +63,22 @@ print_counts(perf_event_desc_t *fds, int num, int do_delta) uint64_t val; double ratio; - ret = read(fds[i].fd, values, sizeof(values)); - if (ret < (ssize_t)sizeof(values)) { + ret = read(fds[i].fd, fds[i].values, sizeof(fds[i].values)); + if (ret < (ssize_t)sizeof(fds[i].values)) { if (ret == -1) err(1, "cannot read values event %s", fds[i].name); else warnx("could not read event%d", i); } - /* - * scaling because we may be sharing the PMU and - * thus may be multiplexed - */ - fds[i].prev_value = fds[i].value; - fds[i].value = val = perf_scale(values); - ratio = perf_scale_ratio(values); + val = perf_scale(fds[i].values); + ratio = perf_scale_ratio(fds[i].values); - val = do_delta ? (val - fds[i].prev_value): val; + val = do_delta ? perf_scale_delta(fds[i].values, fds[i].prev_values) : val; + + fds[i].prev_values[0] = fds[i].values[0]; + fds[i].prev_values[1] = fds[i].values[1]; + fds[i].prev_values[2] = fds[i].values[2]; if (ratio == 1.0) printf("%20"PRIu64" %s\n", val, fds[i].name); @@ -89,7 +87,6 @@ print_counts(perf_event_desc_t *fds, int num, int do_delta) printf("%20"PRIu64" %s (did not run: incompatible events, too many events in a group, competing session)\n", val, fds[i].name); else printf("%20"PRIu64" %s (scaled from %.2f%% of time)\n", val, fds[i].name, ratio*100.0); - } } diff --git a/src/libpfm4/perf_examples/task_cpu.c b/src/libpfm4/perf_examples/task_cpu.c index 3cb7915..52d6938 100644 --- a/src/libpfm4/perf_examples/task_cpu.c +++ b/src/libpfm4/perf_examples/task_cpu.c @@ -123,10 +123,9 @@ read_groups(perf_event_desc_t *fds, int num) * scaling because we may be sharing the PMU and * thus may be multiplexed */ - fds[i].prev_value = fds[i].value; - fds[i].value = perf_scale(values); - fds[i].enabled = values[1]; - fds[i].running = values[2]; + fds[i].values[0] = values[0]; + fds[i].values[1] = values[1]; + fds[i].values[2] = values[2]; } evt += num_evts_to_read; } @@ -137,35 +136,38 @@ read_groups(perf_event_desc_t *fds, int num) static void print_counts(perf_event_desc_t *fds, int num, int cpu) { + double ratio; + uint64_t val, delta; int i; read_groups(fds, num); for(i=0; i < num; i++) { - double ratio; - uint64_t val; - - val = fds[i].value - fds[i].prev_value; - - ratio = 0.0; - if (fds[i].enabled) - ratio = 1.0 * fds[i].running / fds[i].enabled; + val = perf_scale(fds[i].values); + delta = perf_scale_delta(fds[i].values, fds[i].prev_values); + ratio = perf_scale_ratio(fds[i].values); /* separate groups */ if (perf_is_group_leader(fds, i)) putchar('\n'); - if (fds[i].value < fds[i].prev_value) { - printf("inconsistent scaling %s (cur=%'"PRIu64" : prev=%'"PRIu64")\n", fds[i].name, fds[i].value, fds[i].prev_value); - continue; - } - printf("CPU%-2d %'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", - cpu, - val, - fds[i].name, - (1.0-ratio)*100.0, - fds[i].enabled, - fds[i].running); + if (options.print) + printf("CPU%-2d %'20"PRIu64" %'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", + cpu, + val, + delta, + fds[i].name, + (1.0-ratio)*100.0, + fds[i].values[1], + fds[i].values[2]); + else + printf("CPU%-2d %'20"PRIu64" %s (%.2f%% scaling, ena=%'"PRIu64", run=%'"PRIu64")\n", + cpu, + val, + fds[i].name, + (1.0-ratio)*100.0, + fds[i].values[1], + fds[i].values[2]); } } @@ -183,6 +185,8 @@ parent(char **arg) char buf; pid_t pid; + go[0] = go[1] = -1; + if (pfm_initialize() != PFM_SUCCESS) errx(1, "libpfm initialization failed"); @@ -290,7 +294,7 @@ parent(char **arg) } } - if (!options.pid) + if (!options.pid && go[1] > -1) close(go[1]); if (options.print) { diff --git a/src/libpfm4/perf_examples/task_smpl.c b/src/libpfm4/perf_examples/task_smpl.c index 1029f7b..3180458 100644 --- a/src/libpfm4/perf_examples/task_smpl.c +++ b/src/libpfm4/perf_examples/task_smpl.c @@ -270,7 +270,7 @@ mainloop(char **arg) * We are skipping the first 3 values (nr, time_enabled, time_running) * and then for each event we get a pair of values. */ - if (num_fds > 1) { + if (num_fds > 1 && fds[0].fd > -1) { sz = (3+2*num_fds)*sizeof(uint64_t); val = malloc(sz); if (!val) diff --git a/src/libpfm4/python/Makefile b/src/libpfm4/python/Makefile index 7af9a94..d286bd4 100644 --- a/src/libpfm4/python/Makefile +++ b/src/libpfm4/python/Makefile @@ -28,10 +28,10 @@ include $(TOPDIR)/rules.mk PYTHON_PREFIX=$(PREFIX) all: - ./setup.py build + CFLAGS="-O2 -g" ./setup.py build install: - ./setup.py install --prefix=$(DESTDIR)$(PYTHON_PREFIX) + CFLAGS="-O2 -g" ./setup.py install --prefix=$(DESTDIR)$(PYTHON_PREFIX) clean: $(RM) src/perfmon_int_wrap.c src/perfmon_int.py src/*.pyc diff --git a/src/libpfm4/tests/validate_arm.c b/src/libpfm4/tests/validate_arm.c index d1d6ab2..2a6f420 100644 --- a/src/libpfm4/tests/validate_arm.c +++ b/src/libpfm4/tests/validate_arm.c @@ -83,7 +83,30 @@ static const test_event_t arm_test_events[]={ .codes[0] = 0x40, .fstr = "arm_ac9::JAVA_HW_BYTECODE_EXEC", }, - + { .name = "arm_ac15::CPU_CYCLES", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x8000011, + .fstr = "arm_ac15::CPU_CYCLES:k=1:u=1:hv=0", + }, + { .name = "arm_ac15::CPU_CYCLES:k", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x88000011, + .fstr = "arm_ac15::CPU_CYCLES:k=1:u=0:hv=0", + }, + { .name = "arm_ac15::CPU_CYCLES:k:u", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x8000011, + .fstr = "arm_ac15::CPU_CYCLES:k=1:u=1:hv=0", + }, + { .name = "arm_ac15::INST_RETIRED", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x8000008, + .fstr = "arm_ac15::INST_RETIRED:k=1:u=1:hv=0", + }, }; #define NUM_TEST_EVENTS (int)(sizeof(arm_test_events)/sizeof(test_event_t)) diff --git a/src/libpfm4/tests/validate_x86.c b/src/libpfm4/tests/validate_x86.c index 1ac7dbf..7b77f00 100644 --- a/src/libpfm4/tests/validate_x86.c +++ b/src/libpfm4/tests/validate_x86.c @@ -36,949 +36,1464 @@ #include #define MAX_ENCODING 8 +#define SRC_LINE .line = __LINE__ typedef struct { const char *name; const char *fstr; uint64_t codes[MAX_ENCODING]; int ret, count; + int line; } test_event_t; static const test_event_t x86_test_events[]={ - { .name = "core::INST_RETIRED:ANY_P", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c0ull, }, - { .name = "core::INST_RETIRED:ANY_P:ANY_P", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:ANY_P", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c0ull, }, - { .name = "core::INST_RETIRED:ANY_P:DEAD", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:DEAD", .ret = PFM_ERR_ATTR, /* cannot know if it is umask or mod */ .count = 0, .codes[0] = 0ull, }, - { .name = "core::INST_RETIRED:ANY_P:u:u", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:u:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5100c0ull, }, - { .name = "core::INST_RETIRED:ANY_P:u=0:k=1:u=1", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:u=0:k=1:u=1", .ret = PFM_ERR_ATTR_SET, .count = 0, .codes[0] = 0ull, }, - { .name = "core::INST_RETIRED:ANY_P:c=1:i", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300c0ull, }, - { .name = "core::INST_RETIRED:ANY_P:c=1:i=1", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:c=1:i=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300c0ull, }, - { .name = "core::INST_RETIRED:ANY_P:c=2", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:c=2", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x25300c0ull, }, - { .name = "core::INST_RETIRED:ANY_P:c=320", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:c=320", .ret = PFM_ERR_ATTR_VAL, .count = 0, .codes[0] = 0ull, }, - { .name = "core::INST_RETIRED:ANY_P:t=1", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:t=1", .ret = PFM_ERR_ATTR, .count = 0, .codes[0] = 0ull, }, - { .name = "core::L2_LINES_IN", + { SRC_LINE, + .name = "core::L2_LINES_IN", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537024ull, }, - { .name = "core::L2_LINES_IN:SELF", + { SRC_LINE, + .name = "core::L2_LINES_IN:SELF", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537024ull, .fstr = "core::L2_LINES_IN:SELF:ANY:k=1:u=1:e=0:i=0:c=0", }, - { .name = "core::L2_LINES_IN:SELF:BOTH_CORES", + { SRC_LINE, + .name = "core::L2_LINES_IN:SELF:BOTH_CORES", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, - { .name = "core::L2_LINES_IN:SELF:PREFETCH", + { SRC_LINE, + .name = "core::L2_LINES_IN:SELF:PREFETCH", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x535024ull, }, - { .name = "core::L2_LINES_IN:SELF:PREFETCH:ANY", + { SRC_LINE, + .name = "core::L2_LINES_IN:SELF:PREFETCH:ANY", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, - { .name = "core::RS_UOPS_DISPATCHED_NONE", + { SRC_LINE, + .name = "core::RS_UOPS_DISPATCHED_NONE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300a0ull, }, - { .name = "core::RS_UOPS_DISPATCHED_NONE:c=2", + { SRC_LINE, + .name = "core::RS_UOPS_DISPATCHED_NONE:c=2", .ret = PFM_ERR_ATTR_SET, .count = 1, .codes[0] = 0ull, }, - { .name = "core::branch_instructions_retired", + { SRC_LINE, + .name = "core::branch_instructions_retired", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c4ull, .fstr = "core::BR_INST_RETIRED:ANY:k=1:u=1:e=0:i=0:c=0" }, - { .name = "nhm::branch_instructions_retired", + { SRC_LINE, + .name = "nhm::branch_instructions_retired", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c4ull, .fstr = "nhm::BR_INST_RETIRED:ALL_BRANCHES:k=1:u=1:e=0:i=0:c=0:t=0" }, - { .name = "wsm::BRANCH_INSTRUCTIONS_RETIRED", + { SRC_LINE, + .name = "wsm::BRANCH_INSTRUCTIONS_RETIRED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c4ull, /* architected encoding, guaranteed to exist */ .fstr = "wsm::BR_INST_RETIRED:ALL_BRANCHES:k=1:u=1:e=0:i=0:c=0:t=0" }, - { .name = "nhm::ARITH:DIV:k", + { SRC_LINE, + .name = "nhm::ARITH:DIV:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d60114ull, .fstr = "nhm::ARITH:CYCLES_DIV_BUSY:k=1:u=0:e=1:i=1:c=1:t=0", }, - { .name = "nhm::ARITH:CYCLES_DIV_BUSY:k=1:u=1:e=1:i=1:c=1:t=0", + { SRC_LINE, + .name = "nhm::ARITH:CYCLES_DIV_BUSY:k=1:u=1:e=1:i=1:c=1:t=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d70114ull, .fstr = "nhm::ARITH:CYCLES_DIV_BUSY:k=1:u=1:e=1:i=1:c=1:t=0", }, - { .name = "wsm::UOPS_EXECUTED:CORE_STALL_COUNT:u", + { SRC_LINE, + .name = "wsm::UOPS_EXECUTED:CORE_STALL_COUNT:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1f53fb1ull, .fstr = "wsm::UOPS_EXECUTED:CORE_STALL_CYCLES:k=0:u=1:e=1:i=1:c=1:t=1", }, - { .name = "wsm::UOPS_EXECUTED:CORE_STALL_COUNT:u:t=0", + { SRC_LINE, + .name = "wsm::UOPS_EXECUTED:CORE_STALL_COUNT:u:t=0", .ret = PFM_ERR_ATTR_SET, .count = 0, .codes[0] = 0ull, }, - { .name = "wsm_unc::unc_qmc_writes:full_any:partial_any", + { SRC_LINE, + .name = "wsm_unc::unc_qmc_writes:full_any:partial_any", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, - { .name = "wsm_unc::unc_qmc_writes", + { SRC_LINE, + .name = "wsm_unc::unc_qmc_writes", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50072full, .fstr = "wsm_unc::UNC_QMC_WRITES:FULL_ANY:e=0:i=0:c=0:o=0", }, - { .name = "wsm_unc::unc_qmc_writes:full_any", + { SRC_LINE, + .name = "wsm_unc::unc_qmc_writes:full_any", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50072full, .fstr = "wsm_unc::UNC_QMC_WRITES:FULL_ANY:e=0:i=0:c=0:o=0", }, - { .name = "wsm_unc::unc_qmc_writes:full_ch0", + { SRC_LINE, + .name = "wsm_unc::unc_qmc_writes:full_ch0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50012full, .fstr = "wsm_unc::UNC_QMC_WRITES:FULL_CH0:e=0:i=0:c=0:o=0", }, - { .name = "wsm_unc::unc_qmc_writes:partial_any", + { SRC_LINE, + .name = "wsm_unc::unc_qmc_writes:partial_any", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50382full, .fstr = "wsm_unc::UNC_QMC_WRITES:PARTIAL_ANY:e=0:i=0:c=0:o=0", }, - { .name = "wsm_unc::unc_qmc_writes:partial_ch0", + { SRC_LINE, + .name = "wsm_unc::unc_qmc_writes:partial_ch0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50082full, .fstr = "wsm_unc::UNC_QMC_WRITES:PARTIAL_CH0:e=0:i=0:c=0:o=0", }, - { .name = "wsm_unc::unc_qmc_writes:partial_ch0:partial_ch1", + { SRC_LINE, + .name = "wsm_unc::unc_qmc_writes:partial_ch0:partial_ch1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x50182full, .fstr = "wsm_unc::UNC_QMC_WRITES:PARTIAL_CH0:PARTIAL_CH1:e=0:i=0:c=0:o=0", }, - { .name = "amd64_fam10h_barcelona::DISPATCHED_FPU", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::DISPATCHED_FPU", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533f00ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, - { .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:k:u=0", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:k:u=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x523f00ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:ALL:k=1:u=0:e=0:i=0:c=0:h=0:g=0" }, - { .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:OPS_ADD:OPS_MULTIPLY", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:OPS_ADD:OPS_MULTIPLY", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530300ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:OPS_ADD:OPS_MULTIPLY:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam10h_barcelona::L2_CACHE_MISS:ALL:DATA", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::L2_CACHE_MISS:ALL:DATA", .ret = PFM_ERR_FEATCOMB, .count = 0, .codes[0] = 0ull, }, - { .name = "amd64_fam10h_barcelona::MEMORY_CONTROLLER_REQUESTS", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::MEMORY_CONTROLLER_REQUESTS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x10053fff0ull, .fstr = "amd64_fam10h_barcelona::MEMORY_CONTROLLER_REQUESTS:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_k8_revb::RETURN_STACK_OVERFLOWS:g=1:u", + { SRC_LINE, + .name = "amd64_k8_revb::RETURN_STACK_OVERFLOWS:g=1:u", .ret = PFM_ERR_ATTR, .count = 0, .codes[0] = 0ull, }, - { .name = "amd64_k8_revb::RETURN_STACK_HITS:e=1", + { SRC_LINE, + .name = "amd64_k8_revb::RETURN_STACK_HITS:e=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x570088ull, .fstr = "amd64_k8_revb::RETURN_STACK_HITS:k=1:u=1:e=1:i=0:c=0", }, - { .name = "amd64_k8_revb::PROBE:ALL", + { SRC_LINE, + .name = "amd64_k8_revb::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533fecull, .fstr = "amd64_k8_revb::PROBE:ALL:k=1:u=1:e=0:i=0:c=0", }, - { .name = "amd64_k8_revc::PROBE:ALL", + { SRC_LINE, + .name = "amd64_k8_revc::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x533fecull, .fstr = "amd64_k8_revc::PROBE:ALL:k=1:u=1:e=0:i=0:c=0", }, - { .name = "amd64_k8_revd::PROBE:ALL", + { SRC_LINE, + .name = "amd64_k8_revd::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_revd::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, - { .name = "amd64_k8_reve::PROBE:ALL", + { SRC_LINE, + .name = "amd64_k8_reve::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_reve::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, - { .name = "amd64_k8_revf::PROBE:ALL", + { SRC_LINE, + .name = "amd64_k8_revf::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_revf::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, - { .name = "amd64_k8_revg::PROBE:ALL", + { SRC_LINE, + .name = "amd64_k8_revg::PROBE:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x537fecull, .fstr = "amd64_k8_revg::PROBE:ALL:k=1:u=1:e=0:i=0:c=0" }, - { .name = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:L2_1G_TLB_HIT", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:L2_1G_TLB_HIT", .ret = PFM_ERR_ATTR, .count = 0, .codes[0] = 0ull, }, - { .name = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530345ull, .fstr = "amd64_fam10h_barcelona::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, - { .name = "amd64_fam10h_shanghai::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", + { SRC_LINE, + .name = "amd64_fam10h_shanghai::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530745ull, .fstr = "amd64_fam10h_shanghai::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, - { .name = "amd64_fam10h_istanbul::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", + { SRC_LINE, + .name = "amd64_fam10h_istanbul::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530745ull, .fstr = "amd64_fam10h_istanbul::L1_DTLB_MISS_AND_L2_DTLB_HIT:ALL:k=1:u=1:e=0:i=0:c=0:h=0:g=0" }, - { .name = "amd64_fam10h_barcelona::READ_REQUEST_TO_L3_CACHE", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::READ_REQUEST_TO_L3_CACHE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40053f7e0ull, .fstr = "amd64_fam10h_barcelona::READ_REQUEST_TO_L3_CACHE:ANY_READ:ALL_CORES:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam10h_shanghai::READ_REQUEST_TO_L3_CACHE", + { SRC_LINE, + .name = "amd64_fam10h_shanghai::READ_REQUEST_TO_L3_CACHE", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40053f7e0ull, .fstr = "amd64_fam10h_shanghai::READ_REQUEST_TO_L3_CACHE:ANY_READ:ALL_CORES:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "core::RAT_STALLS:ANY:u:c=1,cycles", /* must cut at comma */ + { SRC_LINE, + .name = "core::RAT_STALLS:ANY:u:c=1,cycles", /* must cut at comma */ .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1510fd2ull, .fstr = "core::RAT_STALLS:ANY:k=0:u=1:e=0:i=0:c=1" }, - { .name = "wsm::mem_uncore_retired:remote_dram", + { SRC_LINE, + .name = "wsm::mem_uncore_retired:remote_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53200f, .fstr = "wsm::MEM_UNCORE_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm_dp::mem_uncore_retired:remote_dram", + { SRC_LINE, + .name = "wsm_dp::mem_uncore_retired:remote_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53100f, .fstr = "wsm_dp::MEM_UNCORE_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::mem_uncore_retired:local_dram", + { SRC_LINE, + .name = "wsm::mem_uncore_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53100f, .fstr = "wsm::MEM_UNCORE_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm_dp::mem_uncore_retired:local_dram", + { SRC_LINE, + .name = "wsm_dp::mem_uncore_retired:local_dram", .ret = PFM_ERR_ATTR, .count = 1, .codes[0] = 0, }, - { .name = "nhm::mem_uncore_retired:uncacheable", + { SRC_LINE, + .name = "nhm::mem_uncore_retired:uncacheable", .ret = PFM_ERR_ATTR, .count = 1, .codes[0] = 0, }, - { .name = "nhm::mem_uncore_retired:l3_data_miss_unknown", + { SRC_LINE, + .name = "nhm::mem_uncore_retired:l3_data_miss_unknown", .ret = PFM_ERR_ATTR, .count = 1, .codes[0] = 0, }, - { .name = "nhm_ex::mem_uncore_retired:uncacheable", + { SRC_LINE, + .name = "nhm_ex::mem_uncore_retired:uncacheable", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53800f, .fstr = "nhm_ex::MEM_UNCORE_RETIRED:UNCACHEABLE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm_ex::mem_uncore_retired:l3_data_miss_unknown", + { SRC_LINE, + .name = "nhm_ex::mem_uncore_retired:l3_data_miss_unknown", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53010f, .fstr = "nhm_ex::MEM_UNCORE_RETIRED:L3_DATA_MISS_UNKNOWN:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm::mem_uncore_retired:local_dram", + { SRC_LINE, + .name = "nhm::mem_uncore_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53200f, .fstr = "nhm::MEM_UNCORE_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm_ex::mem_uncore_retired:local_dram", + { SRC_LINE, + .name = "nhm_ex::mem_uncore_retired:local_dram", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53200f, .fstr = "nhm_ex::MEM_UNCORE_RETIRED:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_0:k", + { SRC_LINE, + .name = "wsm::offcore_response_0:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5201b7, .codes[1] = 0xffff, .fstr = "wsm::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=0:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_0:local_dram", + { SRC_LINE, + .name = "wsm::offcore_response_0:local_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x20ff, .fstr = "wsm::OFFCORE_RESPONSE_0:ANY_REQUEST:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_0:PF_IFETCH", + { SRC_LINE, + .name = "wsm::offcore_response_0:PF_IFETCH", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xff40, .fstr = "wsm::OFFCORE_RESPONSE_0:PF_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_0:ANY_DATA:LOCAL_DRAM", + { SRC_LINE, + .name = "wsm::offcore_response_0:ANY_DATA:LOCAL_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x2033, .fstr = "wsm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:PF_DATA_RD:PF_RFO:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_0:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", + { SRC_LINE, + .name = "wsm::offcore_response_0:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x6003, .fstr = "wsm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:LOCAL_DRAM:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0" }, - { .name = "wsm::offcore_response_1:local_dram", + { SRC_LINE, + .name = "wsm::offcore_response_1:local_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x20ff, .fstr = "wsm::OFFCORE_RESPONSE_1:ANY_REQUEST:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_1:PF_IFETCH", + { SRC_LINE, + .name = "wsm::offcore_response_1:PF_IFETCH", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0xff40, .fstr = "wsm::OFFCORE_RESPONSE_1:PF_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_1:ANY_DATA:LOCAL_DRAM", + { SRC_LINE, + .name = "wsm::offcore_response_1:ANY_DATA:LOCAL_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x2033, .fstr = "wsm::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:PF_DATA_RD:PF_RFO:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_1:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", + { SRC_LINE, + .name = "wsm::offcore_response_1:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x6003, .fstr = "wsm::OFFCORE_RESPONSE_1:DMND_DATA_RD:DMND_RFO:LOCAL_DRAM:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm::offcore_response_0:ANY_LLC_MISS", + { SRC_LINE, + .name = "wsm::offcore_response_0:ANY_LLC_MISS", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf8ff, .fstr = "wsm::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:LOCAL_DRAM:REMOTE_DRAM:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm_dp::offcore_response_0:ANY_LLC_MISS", + { SRC_LINE, + .name = "wsm_dp::offcore_response_0:ANY_LLC_MISS", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf8ff, .fstr = "wsm_dp::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_CACHE_HITM:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:REMOTE_DRAM:OTHER_LLC_MISS:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm_dp::offcore_response_0:LOCAL_CACHE", + { SRC_LINE, + .name = "wsm_dp::offcore_response_0:LOCAL_CACHE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x7ff, .fstr = "wsm_dp::OFFCORE_RESPONSE_0:ANY_REQUEST:UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "wsm_dp::offcore_response_0:ANY_CACHE_DRAM", + { SRC_LINE, + .name = "wsm_dp::offcore_response_0:ANY_CACHE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x7fff, .fstr = "wsm_dp::OFFCORE_RESPONSE_0:ANY_REQUEST:UNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:REMOTE_DRAM:OTHER_LLC_MISS:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm::offcore_response_0:k", + { SRC_LINE, + .name = "nhm::offcore_response_0:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5201b7, .codes[1] = 0xffff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=0:e=0:i=0:c=0:t=0", }, - { .name = "nhm::offcore_response_0:local_dram", + { SRC_LINE, + .name = "nhm::offcore_response_0:local_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x40ff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm::offcore_response_0:any_llc_miss", + { SRC_LINE, + .name = "nhm::offcore_response_0:any_llc_miss", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xf8ff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm::offcore_response_0:any_dram", + { SRC_LINE, + .name = "nhm::offcore_response_0:any_dram", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x60ff, .fstr = "nhm::OFFCORE_RESPONSE_0:ANY_REQUEST:REMOTE_DRAM:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm::offcore_response_0:PF_IFETCH", + { SRC_LINE, + .name = "nhm::offcore_response_0:PF_IFETCH", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0xff40, .fstr = "nhm::OFFCORE_RESPONSE_0:PF_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm::offcore_response_0:ANY_DATA:LOCAL_DRAM", + { SRC_LINE, + .name = "nhm::offcore_response_0:ANY_DATA:LOCAL_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x4033, .fstr = "nhm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:PF_DATA_RD:PF_RFO:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "nhm::offcore_response_0:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", + { SRC_LINE, + .name = "nhm::offcore_response_0:DMND_RFO:DMND_DATA_RD:LOCAL_DRAM:REMOTE_DRAM", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x6003, .fstr = "nhm::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:REMOTE_DRAM:LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "amd64_k8_revg::DISPATCHED_FPU:0xff:k", + { SRC_LINE, + .name = "amd64_k8_revg::DISPATCHED_FPU:0xff:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x52ff00ull, .fstr = "amd64_k8_revg::DISPATCHED_FPU:0xff:k=1:u=0:e=0:i=0:c=0" }, - { .name = "amd64_k8_revg::DISPATCHED_FPU:0x4ff", + { SRC_LINE, + .name = "amd64_k8_revg::DISPATCHED_FPU:0x4ff", .ret = PFM_ERR_ATTR, .count = 0, }, - { .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:0x4ff:u", + { SRC_LINE, + .name = "amd64_fam10h_barcelona::DISPATCHED_FPU:0x4ff:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x40051ff00ull, .fstr = "amd64_fam10h_barcelona::DISPATCHED_FPU:0x4ff:k=0:u=1:e=0:i=0:c=0:h=0:g=0" }, - { .name = "wsm::inst_retired:0xff:k", + { SRC_LINE, + .name = "wsm::inst_retired:0xff:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x52ffc0, .fstr = "wsm::INST_RETIRED:0xff:k=1:u=0:e=0:i=0:c=0:t=0", }, - { .name = "wsm::uops_issued:0xff:stall_cycles", + { SRC_LINE, + .name = "wsm::uops_issued:0xff:stall_cycles", .ret = PFM_ERR_ATTR, .count = 0, }, - { .name = "wsm::uops_issued:0xff:0xf1", + { SRC_LINE, + .name = "wsm::uops_issued:0xff:0xf1", .ret = PFM_ERR_ATTR, .count = 0, }, - { .name = "wsm::uops_issued:0xff=", + { SRC_LINE, + .name = "wsm::uops_issued:0xff=", .ret = PFM_ERR_ATTR_VAL, .count = 0, }, - { .name = "wsm::uops_issued:123", + { SRC_LINE, + .name = "wsm::uops_issued:123", .ret = PFM_ERR_ATTR, .count = 0, }, - { .name = "wsm::uops_issued:0xfff", + { SRC_LINE, + .name = "wsm::uops_issued:0xfff", .ret = PFM_ERR_ATTR, .count = 0, }, - { .name = "netburst::global_power_events", + { SRC_LINE, + .name = "netburst::global_power_events", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2600020f, .codes[1] = 0x3d000, .fstr = "netburst::global_power_events:RUNNING:k=1:u=1:e=0:cmpl=0:thr=0", }, - { .name = "netburst::global_power_events:RUNNING:u:k", + { SRC_LINE, + .name = "netburst::global_power_events:RUNNING:u:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2600020f, .codes[1] = 0x3d000, .fstr = "netburst::global_power_events:RUNNING:k=1:u=1:e=0:cmpl=0:thr=0", }, - { .name = "netburst::global_power_events:RUNNING:e", + { SRC_LINE, + .name = "netburst::global_power_events:RUNNING:e", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x2600020f, .codes[1] = 0x107d000, .fstr = "netburst::global_power_events:RUNNING:k=1:u=1:e=1:cmpl=0:thr=0", }, - { .name = "netburst::global_power_events:RUNNING:cmpl:e:u", + { SRC_LINE, + .name = "netburst::global_power_events:RUNNING:cmpl:e:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x26000205, .codes[1] = 0x10fd000, .fstr = "netburst::global_power_events:RUNNING:k=0:u=1:e=1:cmpl=1:thr=0", }, - { .name = "netburst::global_power_events:RUNNING:cmpl:thr=8:u", + { SRC_LINE, + .name = "netburst::global_power_events:RUNNING:cmpl:thr=8:u", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x26000205, .codes[1] = 0x8fd000, .fstr = "netburst::global_power_events:RUNNING:k=0:u=1:e=0:cmpl=1:thr=8", }, - { .name = "netburst::global_power_events:RUNNING:cmpl:thr=32:u", + { SRC_LINE, + .name = "netburst::global_power_events:RUNNING:cmpl:thr=32:u", .ret = PFM_ERR_ATTR_VAL, .count = 0, }, - { .name = "netburst::instr_completed:nbogus", + { SRC_LINE, + .name = "netburst::instr_completed:nbogus", .ret = PFM_ERR_NOTFOUND, .count = 0, }, - { .name = "netburst_p::instr_completed:nbogus", + { SRC_LINE, + .name = "netburst_p::instr_completed:nbogus", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0xe00020f, .codes[1] = 0x39000, .fstr = "netburst_p::instr_completed:NBOGUS:k=1:u=1:e=0:cmpl=0:thr=0", }, - { .name = "snb::cpl_cycles:ring0_trans:u", + { SRC_LINE, + .name = "snb::cpl_cycles:ring0_trans:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x155015c, .fstr = "snb::CPL_CYCLES:RING0:k=0:u=1:e=1:i=0:c=1:t=0", }, - { .name = "snb::cpl_cycles:ring0_trans:e=1", + { SRC_LINE, + .name = "snb::cpl_cycles:ring0_trans:e=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x157015cull, }, - { .name = "snb::OFFCORE_REQUESTS_OUTSTanding:ALL_DATA_RD_CYCLES", + { SRC_LINE, + .name = "snb::OFFCORE_REQUESTS_OUTSTanding:ALL_DATA_RD_CYCLES", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1530860, .fstr = "snb::OFFCORE_REQUESTS_OUTSTANDING:ALL_DATA_RD:k=1:u=1:e=0:i=0:c=1:t=0", }, - { .name = "snb::uops_issued:core_stall_cycles:u:k", + { SRC_LINE, + .name = "snb::uops_issued:core_stall_cycles:u:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1f3010e, .fstr = "snb::UOPS_ISSUED:ANY:k=1:u=1:e=0:i=1:c=1:t=1", }, - { .name = "snb::LLC_REFERences:k:t=1", + { SRC_LINE, + .name = "snb::LLC_REFERences:k:t=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x724f2e, .fstr = "snb::LAST_LEVEL_CACHE_REFERENCES:k=1:u=0:e=0:i=0:c=0:t=1", }, - { .name = "snb::ITLB:0x1", + { SRC_LINE, + .name = "snb::ITLB:0x1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301ae, .fstr = "snb::ITLB:0x1:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:DMND_RFO:ANY_RESPONSE", + { SRC_LINE, + .name = "snb::offcore_response_0:DMND_RFO:ANY_RESPONSE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:DMND_RFO:ANY_REQUEST", + { SRC_LINE, + .name = "snb::offcore_response_0:DMND_RFO:ANY_REQUEST", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18fff, }, - { .name = "snb::offcore_response_0:DMND_RFO", + { SRC_LINE, + .name = "snb::offcore_response_0:DMND_RFO", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:any_response", + { SRC_LINE, + .name = "snb::offcore_response_0:any_response", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x18fff, .fstr = "snb::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", + { SRC_LINE, + .name = "snb::offcore_response_0:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x80020060, .fstr = "snb::OFFCORE_RESPONSE_0:PF_RFO:PF_IFETCH:NO_SUPP:SNP_NONE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_1:DMND_RFO:ANY_RESPONSE", + { SRC_LINE, + .name = "snb::offcore_response_1:DMND_RFO:ANY_RESPONSE", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_1:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_1:DMND_RFO:ANY_REQUEST", + { SRC_LINE, + .name = "snb::offcore_response_1:DMND_RFO:ANY_REQUEST", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x18fff, }, - { .name = "snb::offcore_response_1:DMND_RFO", + { SRC_LINE, + .name = "snb::offcore_response_1:DMND_RFO", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x10002, .fstr = "snb::OFFCORE_RESPONSE_1:DMND_RFO:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_1:any_response", + { SRC_LINE, + .name = "snb::offcore_response_1:any_response", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x18fff, .fstr = "snb::OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_1:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", + { SRC_LINE, + .name = "snb::offcore_response_1:NO_SUPP:SNP_NONE:PF_RFO:PF_IFETCH", .count = 2, .codes[0] = 0x5301bb, .codes[1] = 0x80020060, .fstr = "snb::OFFCORE_RESPONSE_1:PF_RFO:PF_IFETCH:NO_SUPP:SNP_NONE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0", + { SRC_LINE, + .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530068, .fstr = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:DC_BUFFER_1", + { SRC_LINE, + .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:DC_BUFFER_1", .ret = PFM_ERR_FEATCOMB, }, - { .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:IC_BUFFER_0", + { SRC_LINE, + .name = "amd64_fam14h_bobcat::MAB_REQUESTS:DC_BUFFER_0:IC_BUFFER_0", .ret = PFM_ERR_FEATCOMB, }, - { .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_DC_BUFFER", + { SRC_LINE, + .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_DC_BUFFER", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530b68, .fstr = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_DC_BUFFER:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER", + { SRC_LINE, + .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530a68, .fstr = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER:IC_BUFFER_1", + { SRC_LINE, + .name = "amd64_fam14h_bobcat::MAB_REQUESTS:ANY_IC_BUFFER:IC_BUFFER_1", .ret = PFM_ERR_FEATCOMB, }, - { .name = "core::INST_RETIRED:ANY_P:e", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, - { .name = "core::INST_RETIRED:ANY_P:e:c=1", + { SRC_LINE, + .name = "core::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, - { .name = "atom::INST_RETIRED:ANY_P:e", + { SRC_LINE, + .name = "atom::INST_RETIRED:ANY_P:e", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5700c0ull, }, - { .name = "atom::INST_RETIRED:ANY_P:e:c=1", + { SRC_LINE, + .name = "atom::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, - { .name = "nhm::INST_RETIRED:ANY_P:e", + { SRC_LINE, + .name = "nhm::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, - { .name = "nhm::INST_RETIRED:ANY_P:e:c=1", + { SRC_LINE, + .name = "nhm::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, - { .name = "wsm::INST_RETIRED:ANY_P:e", + { SRC_LINE, + .name = "wsm::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, - { .name = "wsm::INST_RETIRED:ANY_P:e:c=1", + { SRC_LINE, + .name = "wsm::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, - { .name = "snb::INST_RETIRED:ANY_P:e", + { SRC_LINE, + .name = "snb::INST_RETIRED:ANY_P:e", .ret = PFM_ERR_ATTR, }, - { .name = "snb::INST_RETIRED:ANY_P:e:c=1", + { SRC_LINE, + .name = "snb::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, - { .name = "snb::INST_RETIRED:ANY_P:e:c=1", + { SRC_LINE, + .name = "snb::INST_RETIRED:ANY_P:e:c=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x15700c0ull, }, - { .name = "snb::offcore_response_0:any_request", + { SRC_LINE, + .name = "snb::offcore_response_0:any_request", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]= 0x18fffull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHER:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:dmnd_data_rd", + { SRC_LINE, + .name = "snb::offcore_response_0:dmnd_data_rd", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x10001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite", + { SRC_LINE, + .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x3f80080001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:LLC_HITE:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite:snp_any", + { SRC_LINE, + .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite:snp_any", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x3f80080001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:LLC_HITE:SNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite:hitm", + { SRC_LINE, + .name = "snb::offcore_response_0:dmnd_data_rd:llc_hite:hitm", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x1000080001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:LLC_HITE:HITM:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:dmnd_data_rd:any_response", + { SRC_LINE, + .name = "snb::offcore_response_0:dmnd_data_rd:any_response", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x10001ull, .fstr = "snb::OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::offcore_response_0:dmnd_data_rd:any_response:snp_any", + { SRC_LINE, + .name = "snb::offcore_response_0:dmnd_data_rd:any_response:snp_any", .ret = PFM_ERR_FEATCOMB, }, - { .name = "snb::offcore_response_0:dmnd_data_rd:any_response:llc_hitmesf", + { SRC_LINE, + .name = "snb::offcore_response_0:dmnd_data_rd:any_response:llc_hitmesf", .ret = PFM_ERR_FEATCOMB, }, - { .name = "snb::offcore_response_0:any_response", + { SRC_LINE, + .name = "snb::offcore_response_0:any_response", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7ull, .codes[1]=0x18fffull, .fstr = "snb::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "amd64_fam11h_turion::MAB_REQUESTS:DC_BUFFER_0", + { SRC_LINE, + .name = "amd64_fam11h_turion::MAB_REQUESTS:DC_BUFFER_0", .ret = PFM_ERR_NOTFOUND, }, - { .name = "amd64_fam11h_turion::RETIRED_INSTRUCTIONS", + { SRC_LINE, + .name = "amd64_fam11h_turion::RETIRED_INSTRUCTIONS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5300c0, .fstr = "amd64_fam11h_turion::RETIRED_INSTRUCTIONS:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam11h_turion::RETIRED_UOPS:k", + { SRC_LINE, + .name = "amd64_fam11h_turion::RETIRED_UOPS:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5200c1, .fstr = "amd64_fam11h_turion::RETIRED_UOPS:k=1:u=0:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam11h_turion::CPU_CLK_UNHALTED", + { SRC_LINE, + .name = "amd64_fam11h_turion::CPU_CLK_UNHALTED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530076, .fstr = "amd64_fam11h_turion::CPU_CLK_UNHALTED:k=1:u=1:e=0:i=0:c=0:h=0:g=0", }, - { .name = "amd64_fam11h_turion::RETIRED_UOPS:c=1:i", + { SRC_LINE, + .name = "amd64_fam11h_turion::RETIRED_UOPS:c=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1d300c1, .fstr = "amd64_fam11h_turion::RETIRED_UOPS:k=1:u=1:e=0:i=1:c=1:h=0:g=0", }, - { .name = "ivb::ARITH:FPU_DIV", + { SRC_LINE, + .name = "ivb::ARITH:FPU_DIV", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x1570114, .fstr = "ivb::ARITH:FPU_DIV_ACTIVE:k=1:u=1:e=1:i=0:c=1:t=0", }, - { .name = "ivb::INST_RETIRED:ALL", + { SRC_LINE, + .name = "ivb::INST_RETIRED:ALL", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301c0, .fstr = "ivb::INST_RETIRED:ALL:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::INST_RETIRED:ALL:k", + { SRC_LINE, + .name = "ivb::INST_RETIRED:ALL:k", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5201c0, .fstr = "ivb::INST_RETIRED:ALL:k=1:u=0:e=0:i=0:c=0:t=0", }, - { .name = "ivb::INST_RETIRED:ALL:u", + { SRC_LINE, + .name = "ivb::INST_RETIRED:ALL:u", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5101c0, .fstr = "ivb::INST_RETIRED:ALL:k=0:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::TLB_ACCESS:LOAD_STLB_HIT", + { SRC_LINE, + .name = "ivb::TLB_ACCESS:LOAD_STLB_HIT", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53015f, .fstr = "ivb::TLB_ACCESS:LOAD_STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::MOVE_ELIMINATION:INT_NOT_ELIMINATED", + { SRC_LINE, + .name = "ivb::MOVE_ELIMINATION:INT_NOT_ELIMINATED", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530158, .fstr = "ivb::MOVE_ELIMINATION:INT_NOT_ELIMINATED:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::RESOURCE_STALLS:SB:RS", + { SRC_LINE, + .name = "ivb::RESOURCE_STALLS:SB:RS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x530ca2, .fstr = "ivb::RESOURCE_STALLS:RS:SB:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::RESOURCE_STALLS:ROB:RS", + { SRC_LINE, + .name = "ivb::RESOURCE_STALLS:ROB:RS", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5314a2, .fstr = "ivb::RESOURCE_STALLS:RS:ROB:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::CPU_CLK_UNHALTED:REF_P", + { SRC_LINE, + .name = "ivb::CPU_CLK_UNHALTED:REF_P", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x53013c, .fstr = "ivb::CPU_CLK_UNHALTED:REF_XCLK:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK", + { SRC_LINE, + .name = "ivb::DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x538108, - .fstr = "ivb::DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK:k=1:u=1:e=0:i=0:c=0:t=0", + .fstr = "ivb::DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "ivb::offcore_response_0:k", + { SRC_LINE, + .name = "ivb::offcore_response_0:k", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5201b7, .codes[1] = 0x18fff, .fstr = "ivb::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:k=1:u=0:e=0:i=0:c=0:t=0", }, - { .name = "ivb::offcore_response_0:LLC_MISS_LOCAL", + { SRC_LINE, + .name = "ivb::offcore_response_0:LLC_MISS_LOCAL", .ret = PFM_SUCCESS, .count = 2, .codes[0] = 0x5301b7, .codes[1] = 0x3f80408fffull, .fstr = "ivb::OFFCORE_RESPONSE_0:ANY_REQUEST:LLC_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::l2_lines_in:i:i=1", + { SRC_LINE, + .name = "ivb::DTLB_LOAD_MISSES:STLB_HIT", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x53015f, + .fstr = "ivb::DTLB_LOAD_MISSES:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", + }, + { SRC_LINE, + .name = "snb::l2_lines_in:i:i=1", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xd301f1, .fstr = "snb::L2_LINES_IN:I:k=1:u=1:e=0:i=1:c=0:t=0", }, - { .name = "snb::l2_lines_in:i=1:i", + { SRC_LINE, + .name = "snb::l2_lines_in:i=1:i", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xd301f1, .fstr = "snb::L2_LINES_IN:I:k=1:u=1:e=0:i=1:c=0:t=0", }, - { .name = "snb::l2_lines_in:i:i=0", + { SRC_LINE, + .name = "snb::l2_lines_in:i:i=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5301f1, .fstr = "snb::L2_LINES_IN:I:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::l2_lines_in:e:e=0", + { SRC_LINE, + .name = "snb::l2_lines_in:e:e=0", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0x5304f1, .fstr = "snb::L2_LINES_IN:E:k=1:u=1:e=0:i=0:c=0:t=0", }, - { .name = "snb::l2_lines_in:e:e=1", + { SRC_LINE, + .name = "snb::l2_lines_in:e:e=1", .ret = PFM_ERR_ATTR, .count = 0, }, - { .name = "snb::l2_lines_in:e:e=1:c=10", + { SRC_LINE, + .name = "snb::l2_lines_in:e:e=1:c=10", .ret = PFM_SUCCESS, .count = 1, .codes[0] = 0xa5704f1, .fstr = "snb::L2_LINES_IN:E:k=1:u=1:e=1:i=0:c=10:t=0", }, + { SRC_LINE, + .name = "snb_unc_cbo0::unc_clockticks", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x5000ff, + .fstr = "snb_unc_cbo0::UNC_CLOCKTICKS", + }, + { SRC_LINE, + .name = "snb_unc_cbo1::unc_clockticks", + .ret = PFM_ERR_NOTFOUND + }, + { SRC_LINE, + .name = "snb_unc_cbo2::unc_clockticks", + .ret = PFM_ERR_NOTFOUND + }, + { SRC_LINE, + .name = "snb_unc_cbo3::unc_clockticks", + .ret = PFM_ERR_NOTFOUND + }, + { SRC_LINE, + .name = "snb_unc_cbo1::UNC_CBO_CACHE_LOOKUP:STATE_MESI:READ_FILTER:c=1:i", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1d01f34, + .fstr = "snb_unc_cbo1::UNC_CBO_CACHE_LOOKUP:STATE_MESI:READ_FILTER:e=0:i=1:c=1", + }, + { SRC_LINE, + .name = "snbep_unc_cbo1::UNC_C_CLOCKTICKS:u", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "snbep_unc_cbo0::UNC_C_CLOCKTICKS", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0x334, + .codes[1] = 0x7c0000, + .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIF:e=0:i=0:t=0:tf=0:nf=0", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:tid=1", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0x4134, + .codes[1] = 0x7c0c00, + .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_MESIF:e=0:i=0:t=0:tf=0:nf=3", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:nf=3", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0x4134, + .codes[1] = 0x200c00, + .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:e=0:i=0:t=0:tf=0:nf=3", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3:tid=1", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE", + .ret = PFM_ERR_UMASK, + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:WB", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1035, + .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:i=0:t=0:tf=0:nf=0", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0x135, + .codes[1] = 0xca000000, + .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:e=0:i=0:t=0:tf=0:nf=0", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:nf=1", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:nf=1", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0x4135, + .codes[1] = 0xcf000400, + .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:e=0:i=0:t=0:tf=0:nf=1", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPC_RFO:NID_OPCODE:nf=1", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0x4135, + .codes[1] = 0xc0000400, + .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:e=0:i=0:t=0:tf=0:nf=1", + }, + { SRC_LINE, + .name = "snbep_unc_ha::UNC_H_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x0, + .fstr = "snbep_unc_ha::UNC_H_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_ha::UNC_H_REQUESTS:READS:t=1", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1000301, + .fstr = "snbep_unc_ha::UNC_H_REQUESTS:READS:e=0:i=0:t=1", + }, + { SRC_LINE, + .name = "snbep_unc_imc0::UNC_M_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xff, + .fstr = "snbep_unc_imc0::UNC_M_CLOCKTICKS", + }, + { SRC_LINE, + .name = "snbep_unc_imc0::UNC_M_CLOCKTICKS:t=1", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_imc0::UNC_M_CAS_COUNT:RD", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x0304, + .fstr = "snbep_unc_imc0::UNC_M_CAS_COUNT:RD:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_imc0::UNC_M_CAS_COUNT:WR", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xc04, + .fstr = "snbep_unc_imc0::UNC_M_CAS_COUNT:WR:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x0, + .fstr = "snbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_CLOCKTICKS:t=1", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1000000, + .fstr = "snbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=1", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:C6", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x200303, + .fstr = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:C6:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0xb, + .codes[1] = 0x20, + .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=0:t=0:ff=32", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:ff=16", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0xc, + .codes[1] = 0x1000, + .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:e=0:i=0:t=0:ff=16", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:ff=8", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0xd, + .codes[1] = 0x80000, + .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:e=0:i=0:t=0:ff=8", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:ff=40", + .ret = PFM_SUCCESS, + .count = 2, + .codes[0] = 0xe, + .codes[1] = 0x28000000, + .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:e=0:i=0:t=0:ff=40", + }, + { SRC_LINE, + .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x4080, + .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x8080, + .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xc080, + .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:i", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x40004080, + .fstr = "snbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:i=1:t=0" + }, + { SRC_LINE, + .name = "snbep_unc_qpi0::UNC_Q_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x14, + .fstr = "snbep_unc_qpi0::UNC_Q_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x201, + .fstr = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:t=1:i", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1800101, + .fstr = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:e=0:i=1:t=1", + }, + { SRC_LINE, + .name = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x200, + .fstr = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x200602, + .fstr = "snbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x200600, + .fstr = "snbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_ubo::UNC_U_LOCK_CYCLES", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x44, + .fstr = "snbep_unc_ubo::UNC_U_LOCK_CYCLES:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_r2pcie::UNC_R2_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "snbep_unc_r2pcie::UNC_R2_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_r2pcie::UNC_R2_RING_AD_USED:ANY", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xf07, + .fstr = "snbep_unc_r2pcie::UNC_R2_RING_AD_USED:ANY:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_r3qpi0::UNC_R3_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "snbep_unc_r3qpi0::UNC_R3_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x25, + .fstr = "snbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_r3qpi1::UNC_R3_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "snbep_unc_r3qpi1::UNC_R3_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x25, + .fstr = "snbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:i=0:t=0", + }, }; #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t)) @@ -997,35 +1512,35 @@ static int check_test_events(FILE *fp) fstr = NULL; ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); if (ret != e->ret) { - fprintf(fp,"Event%d %s, ret=%s(%d) expected %s(%d)\n", i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); + fprintf(fp,"Line %d, Event%d %s, ret=%s(%d) expected %s(%d)\n", e->line, i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); errors++; } else { if (ret != PFM_SUCCESS) { if (fstr) { - fprintf(fp,"Event%d %s, expected fstr NULL but it is not\n", i, e->name); + fprintf(fp,"Line %d, Event%d %s, expected fstr NULL but it is not\n", e->line, i, e->name); errors++; } if (count != 0) { - fprintf(fp,"Event%d %s, expected count=0 instead of %d\n", i, e->name, count); + fprintf(fp,"Line %d, Event%d %s, expected count=0 instead of %d\n", e->line, i, e->name, count); errors++; } if (codes) { - fprintf(fp,"Event%d %s, expected codes[] NULL but it is not\n", i, e->name); + fprintf(fp,"Line %d, Event%d %s, expected codes[] NULL but it is not\n", e->line, i, e->name); errors++; } } else { if (count != e->count) { - fprintf(fp,"Event%d %s, count=%d expected %d\n", i, e->name, count, e->count); + fprintf(fp,"Line %d, Event%d %s, count=%d expected %d\n", e->line, i, e->name, count, e->count); errors++; } for (j=0; j < count; j++) { if (codes[j] != e->codes[j]) { - fprintf(fp,"Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", i, e->name, j, codes[j], e->codes[j]); + fprintf(fp,"Line %d, Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", e->line, i, e->name, j, codes[j], e->codes[j]); errors++; } } if (e->fstr && strcmp(fstr, e->fstr)) { - fprintf(fp,"Event%d %s, fstr=%s expected %s\n", i, e->name, fstr, e->fstr); + fprintf(fp,"Line %d, Event%d %s, fstr=%s expected %s\n", e->line, i, e->name, fstr, e->fstr); errors++; } } diff --git a/src/papi.c b/src/papi.c index dfc53a6..801d29f 100644 --- a/src/papi.c +++ b/src/papi.c @@ -1345,6 +1345,9 @@ PAPI_enum_cmp_event( int *EventCode, int modifier, int cidx ) return PAPI_OK; } } else if ( IS_NATIVE(i) ) { +// if (!_papi_hwd[cidx]->cmp_info.disabled) { +// return PAPI_ENOEVNT +// } /* Should we check against num native events here? */ event_code=_papi_hwi_eventcode_to_native(*EventCode); retval = _papi_hwd[cidx]->ntv_enum_events((unsigned int *)&event_code, modifier ); @@ -2274,8 +2277,9 @@ PAPI_stop( int EventSet, long long *values ) #if defined(DEBUG) if ( _papi_hwi_debug & DEBUG_API ) { int i; - for ( i = 0; i < ESI->NumberOfEvents; i++ ) + for ( i = 0; i < ESI->NumberOfEvents; i++ ) { APIDBG( "PAPI_stop ESI->sw_stop[%d]:\t%llu\n", i, ESI->sw_stop[i] ); + } } #endif @@ -2467,8 +2471,9 @@ PAPI_read( int EventSet, long long *values ) #if defined(DEBUG) if ( ISLEVEL( DEBUG_API ) ) { int i; - for ( i = 0; i < ESI->NumberOfEvents; i++ ) + for ( i = 0; i < ESI->NumberOfEvents; i++ ) { APIDBG( "PAPI_read values[%d]:\t%lld\n", i, values[i] ); + } } #endif @@ -2558,8 +2563,9 @@ PAPI_read_ts( int EventSet, long long *values, long long *cycles ) #if defined(DEBUG) if ( ISLEVEL( DEBUG_API ) ) { int i; - for ( i = 0; i < ESI->NumberOfEvents; i++ ) + for ( i = 0; i < ESI->NumberOfEvents; i++ ) { APIDBG( "PAPI_read values[%d]:\t%lld\n", i, values[i] ); + } } #endif diff --git a/src/papi.h b/src/papi.h index f81a6fa..08691ff 100644 --- a/src/papi.h +++ b/src/papi.h @@ -217,7 +217,7 @@ /* This is the official PAPI version */ /* The final digit represents the patch count */ -#define PAPI_VERSION PAPI_VERSION_NUMBER(5,0,0,0) +#define PAPI_VERSION PAPI_VERSION_NUMBER(5,0,1,0) #define PAPI_VER_CURRENT (PAPI_VERSION & 0xffff0000) /* Tests for checking event code type */ @@ -1020,7 +1020,6 @@ enum { int PAPI_cleanup_eventset(int EventSet); /**< remove all PAPI events from an event set */ int PAPI_create_eventset(int *EventSet); /**< create a new empty PAPI event set */ int PAPI_detach(int EventSet); /**< detach specified event set from a previously specified process or thread id */ - char *PAPI_descr_error(int); /**< return a pointer to the error message corresponding to a specified error code */ int PAPI_destroy_eventset(int *EventSet); /**< deallocates memory associated with an empty PAPI event set */ int PAPI_enum_event(int *EventCode, int modifier); /**< return the event code for the next available preset or natvie event */ int PAPI_enum_cmp_event(int *EventCode, int modifier, int cidx); /**< return the event code for the next available component event */ @@ -1049,7 +1048,6 @@ enum { int PAPI_list_threads(unsigned long *tids, int *number); /**< list the thread ids currently known to PAPI */ int PAPI_lock(int); /**< lock one of two PAPI internal user mutex variables */ int PAPI_multiplex_init(void); /**< initialize multiplex support in the PAPI library */ - int PAPI_num_hwctrs(void); /**< return the number of hardware counters for the cpu */ int PAPI_num_cmp_hwctrs(int cidx); /**< return the number of hardware counters for a specified component */ int PAPI_num_events(int EventSet); /**< return the number of events in an event set */ int PAPI_overflow(int EventSet, int EventCode, int threshold, @@ -1116,8 +1114,9 @@ enum { /* Backwards compatibility hacks. Remove eventually? */ -int PAPI_num_hwctrs(void); /* for backward compatibility. Don't use! */ +int PAPI_num_hwctrs(void); /**< return the number of hardware counters for the cpu. for backward compatibility. Don't use! */ #define PAPI_COMPONENT_INDEX(a) PAPI_get_event_component(a) +#define PAPI_descr_error(a) PAPI_strerror(a) #ifdef __cplusplus } diff --git a/src/papi_events.csv b/src/papi_events.csv index c42f693..27b6ba9 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -565,8 +565,6 @@ PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:NOT_TAKEN PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:NOT_TAKEN PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES -PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL -PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:ALL_BRANCHES PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_MISP_RETIRED:ALL_BRANCHES # @@ -583,6 +581,8 @@ CPU,snb_ep # PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFO_ANY PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_RD_HIT,L2_RQSTS:RFO_HITS +PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL +PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK # # Counts scalars only; no SSE or AVX is counted; includes speculative @@ -598,7 +598,9 @@ PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|2|*|N1|4|*|+|,FP_COMP_OPS_EXE:SSE_FP_PACKE CPU,ivb # PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:ALL_RFO -PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:DEMAND_DATA_RD_HIT,L2_RQSTS:RFO_HITS +PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:DEMAND_DATA_RD_HIT,L2_RQSTS:RFO_HIT +PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND +PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK # CPU,Intel Core2 diff --git a/src/papi_internal.c b/src/papi_internal.c index 29dd0bf..3c5c3f8 100644 --- a/src/papi_internal.c +++ b/src/papi_internal.c @@ -399,6 +399,8 @@ _papi_hwi_eventcode_to_native(int event_code) { result=_papi_native_events[event_index].component_event; + SUBDBG("Found result %x\n",result); + return result; } @@ -647,7 +649,7 @@ _papi_hwi_assign_eventset( EventSetInfo_t *ESI, int cidx ) ESI->EventInfoArray[i].ops = NULL; ESI->EventInfoArray[i].derived=NOT_DERIVED; for ( j = 0; j < PAPI_EVENTS_IN_DERIVED_EVENT; j++ ) { - ESI->EventInfoArray[i].pos[j] = -1; + ESI->EventInfoArray[i].pos[j] = PAPI_NULL; } } @@ -893,7 +895,6 @@ _papi_hwi_map_events_to_native( EventSetInfo_t *ESI) APIDBG("Mapping %d events in EventSet %d\n", total_events,ESI->EventSetIndex); - event = 0; for( i = 0; i < total_events; i++ ) { @@ -914,10 +915,15 @@ _papi_hwi_map_events_to_native( EventSetInfo_t *ESI) break; } + APIDBG("Loking for subevent %x\n",nevt); + /* Match each sub-event to something in the Native List */ for( n = 0; n < ESI->NativeCount; n++ ) { if ( _papi_hwi_eventcode_to_native(nevt) == ESI->NativeInfoArray[n].ni_event ) { + APIDBG("Found event %x at position %d\n", + nevt, + ESI->NativeInfoArray[n].ni_position); ESI->EventInfoArray[event].pos[k] = ESI->NativeInfoArray[n].ni_position; break; } @@ -1417,7 +1423,7 @@ _papi_hwi_remove_event( EventSetInfo_t * ESI, int EventCode ) return PAPI_ENOEVNT; /* Remove the preset event. */ - for ( j = 0; _papi_hwi_presets[preset_index].code[j] != 0; + for ( j = 0; _papi_hwi_presets[preset_index].code[j] != (unsigned int)PAPI_NULL; j++ ); retval = remove_native_events( ESI, (int *)_papi_hwi_presets[preset_index].code, j ); @@ -1460,7 +1466,7 @@ _papi_hwi_remove_event( EventSetInfo_t * ESI, int EventCode ) array[thisindex].event_code = ( unsigned int ) PAPI_NULL; for ( j = 0; j < PAPI_EVENTS_IN_DERIVED_EVENT; j++ ) - array[thisindex].pos[j] = -1; + array[thisindex].pos[j] = PAPI_NULL; array[thisindex].ops = NULL; array[thisindex].derived = NOT_DERIVED; ESI->NumberOfEvents--; @@ -1560,7 +1566,7 @@ _papi_hwi_cleanup_eventset( EventSetInfo_t * ESI ) /* do we really need to do this, seeing as we free() it later? */ ESI->EventInfoArray[i].event_code= ( unsigned int ) PAPI_NULL; for( j = 0; j < PAPI_EVENTS_IN_DERIVED_EVENT; j++ ) { - ESI->EventInfoArray[i].pos[j] = -1; + ESI->EventInfoArray[i].pos[j] = PAPI_NULL; } ESI->EventInfoArray[i].ops = NULL; ESI->EventInfoArray[i].derived = NOT_DERIVED; diff --git a/src/papi_libpfm4_events.c b/src/papi_libpfm4_events.c index 1279cc5..e7a6966 100644 --- a/src/papi_libpfm4_events.c +++ b/src/papi_libpfm4_events.c @@ -69,7 +69,7 @@ static int find_existing_event(char *name) { } _papi_hwi_unlock( NAMELIB_LOCK ); - if (event<0) SUBDBG("%s not allocated yet\n",name); + if (event<0) { SUBDBG("%s not allocated yet\n",name); } return event; } @@ -124,7 +124,6 @@ static int find_event_no_aliases(char *name) { memset(&pinfo,0,sizeof(pfm_pmu_info_t)); pfm_get_pmu_info(j, &pinfo); if (!pinfo.is_present) { - SUBDBG("PMU %d not present, skipping...\n",j); continue; } @@ -1350,7 +1349,6 @@ _papi_libpfm4_init(papi_vector_t *my_vector, int cidx) { memset(&pinfo,0,sizeof(pfm_pmu_info_t)); retval=pfm_get_pmu_info(i, &pinfo); if (retval!=PFM_SUCCESS) { - SUBDBG("%d\n",retval); continue; } if (pinfo.is_present) { diff --git a/src/papi_memory.c b/src/papi_memory.c index c452c01..19d1b0c 100644 --- a/src/papi_memory.c +++ b/src/papi_memory.c @@ -322,8 +322,9 @@ _papi_mem_cleanup_all( ) } _papi_hwi_unlock( MEMORY_LOCK ); #ifdef DEBUG - if ( cnt ) + if ( 0 != cnt ) { LEAKDBG( "TOTAL MEMORY LEAK: %d bytes.\n", cnt ); + } #endif } diff --git a/src/papi_preset.c b/src/papi_preset.c index 7392db0..6177d1d 100644 --- a/src/papi_preset.c +++ b/src/papi_preset.c @@ -85,7 +85,12 @@ _papi_hwi_setup_all_presets( hwi_search_t * findem, int cidx ) for(k=0;k 0 */ _papi_hwi_presets[insert].count=0; @@ -548,6 +558,8 @@ nextline: if ( table ) { fclose( table ); } + + SUBDBG("Done parsing preset table\n"); return PAPI_OK; } diff --git a/src/perf_events.c b/src/perf_events.c index 6f3c7fa..1c2d989 100644 --- a/src/perf_events.c +++ b/src/perf_events.c @@ -55,6 +55,7 @@ typedef struct { int group_leader_fd; /* fd of group leader */ int event_fd; /* fd of event */ + int event_opened; /* event successfully opened */ uint32_t nr_mmap_pages; /* number pages in the mmap buffer */ void *mmap_buf; /* used for control/profiling */ uint64_t tail; /* current read location in mmap buffer */ @@ -476,6 +477,8 @@ open_pe_events( pe_context_t *ctx, pe_control_t *ctl ) for( i = 0; i < ctl->num_events; i++ ) { + ctl->events[i].event_opened=0; + /* set up the attr structure. We don't set up all fields here */ /* as some have already been set up previously. */ @@ -508,13 +511,12 @@ open_pe_events( pe_context_t *ctx, pe_control_t *ctl ) if ( ctl->events[i].event_fd == -1 ) { SUBDBG("sys_perf_event_open returned error on event #%d." - " Error: %s", + " Error: %s\n", i, strerror( errno ) ); - ret = PAPI_ECNFLCT; goto open_pe_cleanup; } - + SUBDBG ("sys_perf_event_open: tid: %ld, cpu_num: %d," " group_leader/fd: %d, event_fd: %d," " read_format: 0x%"PRIu64"\n", @@ -540,7 +542,7 @@ open_pe_events( pe_context_t *ctx, pe_control_t *ctl ) goto open_pe_cleanup; } } - + ctl->events[i].event_opened=1; } /* Now that we've successfully opened all of the events, do whatever */ @@ -564,7 +566,7 @@ open_pe_events( pe_context_t *ctx, pe_control_t *ctl ) /* Set num_evts only if completely successful */ ctx->state |= PERF_EVENTS_OPENED; - + return PAPI_OK; open_pe_cleanup: @@ -573,7 +575,10 @@ open_pe_cleanup: /* That's probably not strictly necessary. */ while ( i > 0 ) { i--; - if (ctl->events[i].event_fd>=0) close( ctl->events[i].event_fd ); + if (ctl->events[i].event_fd>=0) { + close( ctl->events[i].event_fd ); + ctl->events[i].event_opened=0; + } } return ret; @@ -594,49 +599,56 @@ close_pe_events( pe_context_t *ctx, pe_control_t *ctl ) /* Close child events first */ for( i=0; inum_events; i++ ) { - if (ctl->events[i].group_leader_fd!=-1) { - if ( ctl->events[i].mmap_buf ) { - if ( munmap ( ctl->events[i].mmap_buf, - ctl->events[i].nr_mmap_pages * getpagesize( ) ) ) { - PAPIERROR( "munmap of fd = %d returned error: %s", - ctl->events[i].event_fd, strerror( errno ) ); - return PAPI_ESYS; + if (ctl->events[i].event_opened) { + + if (ctl->events[i].group_leader_fd!=-1) { + if ( ctl->events[i].mmap_buf ) { + if ( munmap ( ctl->events[i].mmap_buf, + ctl->events[i].nr_mmap_pages * getpagesize() ) ) { + PAPIERROR( "munmap of fd = %d returned error: %s", + ctl->events[i].event_fd, strerror( errno ) ); + return PAPI_ESYS; + } } - } - if ( close( ctl->events[i].event_fd ) ) { - PAPIERROR( "close of fd = %d returned error: %s", + if ( close( ctl->events[i].event_fd ) ) { + PAPIERROR( "close of fd = %d returned error: %s", ctl->events[i].event_fd, strerror( errno ) ); - return PAPI_ESYS; - } else { - num_closed++; + return PAPI_ESYS; + } else { + num_closed++; + } + ctl->events[i].event_opened=0; } } - } /* Close the group leaders last */ for( i=0; inum_events; i++ ) { - if (ctl->events[i].group_leader_fd==-1) { - if ( ctl->events[i].mmap_buf ) { - if ( munmap ( ctl->events[i].mmap_buf, - ctl->events[i].nr_mmap_pages * getpagesize( ) ) ) { - PAPIERROR( "munmap of fd = %d returned error: %s", - ctl->events[i].event_fd, strerror( errno ) ); - return PAPI_ESYS; + if (ctl->events[i].event_opened) { + + if (ctl->events[i].group_leader_fd==-1) { + if ( ctl->events[i].mmap_buf ) { + if ( munmap ( ctl->events[i].mmap_buf, + ctl->events[i].nr_mmap_pages * getpagesize() ) ) { + PAPIERROR( "munmap of fd = %d returned error: %s", + ctl->events[i].event_fd, strerror( errno ) ); + return PAPI_ESYS; + } } - } - if ( close( ctl->events[i].event_fd ) ) { - PAPIERROR( "close of fd = %d returned error: %s", + + if ( close( ctl->events[i].event_fd ) ) { + PAPIERROR( "close of fd = %d returned error: %s", ctl->events[i].event_fd, strerror( errno ) ); - return PAPI_ESYS; - } else { - num_closed++; + return PAPI_ESYS; + } else { + num_closed++; + } + ctl->events[i].event_opened=0; } } - } @@ -1259,8 +1271,7 @@ _papi_pe_read( hwd_context_t *ctx, hwd_control_state_t *ctl, SUBDBG("read: fd: %2d, tid: %ld, cpu: %d, ret: %d\n", pe_ctl->events[i].event_fd, (long)pe_ctl->tid, pe_ctl->cpu, ret); - SUBDBG("read: %lld %lld %lld\n",papi_pe_buffer[0], - papi_pe_buffer[1],papi_pe_buffer[2]); + SUBDBG("read: %lld\n",papi_pe_buffer[0]); pe_ctl->counts[i] = papi_pe_buffer[0]; } @@ -1293,8 +1304,12 @@ _papi_pe_read( hwd_context_t *ctx, hwd_control_state_t *ctl, SUBDBG("read: fd: %2d, tid: %ld, cpu: %d, ret: %d\n", pe_ctl->events[0].event_fd, (long)pe_ctl->tid, pe_ctl->cpu, ret); - SUBDBG("read: %lld %lld %lld\n",papi_pe_buffer[0], - papi_pe_buffer[1],papi_pe_buffer[2]); + { + int j; + for(j=0;jnum_events) { diff --git a/src/perfctr-ppc64.c b/src/perfctr-ppc64.c index 80f93db..c088e4c 100644 --- a/src/perfctr-ppc64.c +++ b/src/perfctr-ppc64.c @@ -238,8 +238,9 @@ print_control( const struct perfctr_cpu_control *control ) for ( i = 0; i < ( control->nractrs + control->nrictrs ); ++i ) { SUBDBG( "pmc_map[%u]\t\t%u\n", i, control->pmc_map[i] ); - if ( control->ireset[i] ) + if ( control->ireset[i] ) { SUBDBG( "ireset[%d]\t%X\n", i, control->ireset[i] ); + } } } diff --git a/src/perfctr-x86.c b/src/perfctr-x86.c index f6a7e21..afe86af 100644 --- a/src/perfctr-x86.c +++ b/src/perfctr-x86.c @@ -177,8 +177,9 @@ print_control( const struct perfctr_cpu_control *control ) SUBDBG( "pmc_map[%u]\t\t%u\n", i, control->pmc_map[i] ); } SUBDBG( "evntsel[%u]\t\t0x%08X\n", i, control->evntsel[i] ); - if ( control->ireset[i] ) + if ( control->ireset[i] ) { SUBDBG( "ireset[%u]\t%d\n", i, control->ireset[i] ); + } } } #endif @@ -514,8 +515,9 @@ _bpt_map_shared( hwd_reg_alloc_t * dst, hwd_reg_alloc_t * src ) src->ra_bits.pebs_matrix_vert ) && ( dst->ra_bits.pebs_matrix_vert != src->ra_bits.pebs_matrix_vert ) ) ); - if ( retval2 ) + if ( retval2 ) { SUBDBG( "pebs conflict!\n" ); + } return ( retval1 | retval2 ); } @@ -613,8 +615,9 @@ _x86_allocate_registers( EventSetInfo_t * ESI ) for counter allocation and optimization. */ natNum = ESI->NativeCount; - if ( is_pentium4() ) + if ( is_pentium4() ) { SUBDBG( "native event count: %d\n", natNum ); + } for ( i = 0; i < natNum; i++ ) { /* retrieve the mapping information about this native event */ diff --git a/src/solaris-common.c b/src/solaris-common.c index 31f0ada..4911925 100644 --- a/src/solaris-common.c +++ b/src/solaris-common.c @@ -614,10 +614,12 @@ _solaris_get_system_info( papi_mdi_t *mdi ) int i; name = cpc_getcpuref( cpuver ); - if ( name ) + if ( name ) { SUBDBG( "CPC CPU reference: %s\n", name ); - else + } + else { SUBDBG( "Could not get a CPC CPU reference\n" ); + } for ( i = 0; i < cpc_getnpic( cpuver ); i++ ) { SUBDBG( "\n%6s %-40s %8s\n", "Reg", "Symbolic name", "Code" ); diff --git a/src/solaris-niagara2.c b/src/solaris-niagara2.c index 666b308..1def3bc 100644 --- a/src/solaris-niagara2.c +++ b/src/solaris-niagara2.c @@ -433,20 +433,24 @@ _niagara2_dispatch_timer( int signal, siginfo_t * si, void *info ) SUBDBG( " -> %s: Problems with ESI, not necessarily serious\n", __func__ ); - if ( ESI == NULL ) + if ( ESI == NULL ) { SUBDBG( " -> %s: +++ ESI is NULL\n", __func__ ); + } - if ( ESI->master != thread ) + if ( ESI->master != thread ) { SUBDBG( " -> %s: +++ Thread mismatch, ESI->master=%x thread=%x\n", __func__, ESI->master, thread ); + } - if ( ESI->ctl_state == NULL ) + if ( ESI->ctl_state == NULL ) { SUBDBG( " -> %s: +++ Counter state invalid\n", __func__ ); + } - if ( ( ( ESI->state & PAPI_OVERFLOWING ) == 0 ) ) + if ( ( ( ESI->state & PAPI_OVERFLOWING ) == 0 ) ) { SUBDBG ( " -> %s: +++ Overflow flag missing, ESI->overflow.flags=%x\n", __func__, ESI->overflow.flags ); + } #endif return; @@ -1300,8 +1304,9 @@ _niagara2_update_control_state( hwd_control_state_t * ctrl, } #ifdef DEBUG - if ( i == 0 ) + if ( i == 0 ) { SUBDBG( " -> %s: nothing added\n", __func__ ); + } #endif ctrl->counter_buffer = cpc_buf_create( cpc, ctrl->set ); @@ -1617,8 +1622,9 @@ __cpc_build_ntv_table( void ) #endif #ifdef DEBUG - for ( i = 1; i < __t2_store.pic_ntv_count[0]; i++ ) + for ( i = 1; i < __t2_store.pic_ntv_count[0]; i++ ) { SUBDBG( " -> %s: Event #%d: %s\n", __func__, i, __t2_ntv_events[i] ); + } #endif #ifdef DEBUG diff --git a/src/x86_cpuid_info.c b/src/x86_cpuid_info.c index e30bdc7..a661d25 100644 --- a/src/x86_cpuid_info.c +++ b/src/x86_cpuid_info.c @@ -1335,8 +1335,8 @@ init_intel_leaf4( PAPI_mh_info_t * mh_info, int *num_levels ) break; } - if (cache_selfinit) MEMDBG("\tSelf-init\n"); - if (cache_fullyassoc) MEMDBG("\tFully Associtative\n"); + if (cache_selfinit) { MEMDBG("\tSelf-init\n"); } + if (cache_fullyassoc) { MEMDBG("\tFully Associtative\n"); } //MEMDBG("\tMax logical processors sharing cache: %d\n",cache_maxshare); //MEMDBG("\tMax logical processors sharing package: %d\n",cache_maxpackage);